#ifndef __UTIL_GPIO_H
#define __UTIL_GPIO_H

/******************************  GPIO Pin configuration define  *****************************/
#define PIN_CONFIG_MASK(n)          (0xFu << (4 * (n % 8)))
#define PIN_CONFIG_AIN(n)           (0x0u << (4 * (n % 8)))    // Analog mode
#define PIN_CONFIG_IN_FLOATING(n)   (0x4u << (4 * (n % 8)))    // Floating input (reset state)
#define PIN_CONFIG_IN_PULL(n)       (0x8u << (4 * (n % 8)))    // Input with pull-up / pull-down

#define PIN_CONFIG_OUT_PP_10MHz(n)  (0x1u << (4 * (n % 8)))    // General purpose output push-pull, max speed 10MHz
#define PIN_CONFIG_OUT_PP_2MHz(n)   (0x2u << (4 * (n % 8)))    // General purpose output push-pull, max speed 2MHz
#define PIN_CONFIG_OUT_PP_50MHz(n)  (0x3u << (4 * (n % 8)))    // General purpose output push-pull, max speed 50MHz

#define PIN_CONFIG_OUT_OD_10MHz(n)  (0x5u << (4 * (n % 8)))    // General purpose output Open-drain, max speed 10MHz
#define PIN_CONFIG_OUT_OD_2MHz(n)   (0x6u << (4 * (n % 8)))    // General purpose output Open-drain, max speed 2MHz
#define PIN_CONFIG_OUT_OD_50MHz(n)  (0x7u << (4 * (n % 8)))    // General purpose output Open-drain, max speed 50MHz

#define PIN_CONFIG_AF_PP_10MHz(n)   (0x9u << (4 * (n % 8)))    // Alternate function output Push-pull, max speed 10MHz
#define PIN_CONFIG_AF_PP_2MHz(n)    (0xAu << (4 * (n % 8)))    // Alternate function output Push-pull, max speed 2MHz
#define PIN_CONFIG_AF_PP_50MHz(n)   (0xBu << (4 * (n % 8)))    // Alternate function output Push-pull, max speed 50MHz

#define PIN_CONFIG_AF_OD_10MHz(n)   (0xDu << (4 * (n % 8)))    // Alternate function output Open-drain, max speed 10MHz
#define PIN_CONFIG_AF_OD_2MHz(n)    (0xEu << (4 * (n % 8)))    // Alternate function output Open-drain, max speed 2MHz
#define PIN_CONFIG_AF_OD_50MHz(n)   (0xFu << (4 * (n % 8)))    // Alternate function output Open-drain, max speed 50MHz

/*
  使用示例：
  // 配置 PA1, PA2 为推挽输出模式 最大速度50MHz 【注意小于8的引脚用CRL配置】
  GPIOA->CRL &= ~(PIN_CONFIG_MASK(1) |PIN_CONFIG_MASK(2));
  GPIOA->CRL |= (PIN_CONFIG_OUT_PP_50MHz(1) | PIN_CONFIG_OUT_PP_50MHz(2));

  // 配置 PA8, PA9 为推挽输出模式 最大速度50MHz 【注意大于等于8的引脚用CRH配置】
  GPIOA->CRH &= ~(PIN_CONFIG_MASK(8) |PIN_CONFIG_MASK(9));
  GPIOA->CRH |= (PIN_CONFIG_OUT_PP_50MHz(8) | PIN_CONFIG_OUT_PP_50MHz(9));

  // 配置 PB0, PB1 为上拉输入 【先设置输出高，再配置模式】
  GPIOB->BSRR |= (GPIO_Pin_0 |GPIO_Pin_1);    //上拉
  GPIOB->CRL &= ~(PIN_CONFIG_MASK(0) |PIN_CONFIG_MASK(1));
  GPIOB->CRL |= (PIN_CONFIG_IN_PULL(0) | PIN_CONFIG_IN_PULL(1));
*/






/*******************************  PA0 configuration define *******************************/
#define configPA0_AIN           (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AIN(0))
#define configPA0_IN_FLOATING   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_IN_FLOATING(0))
#define configPA0_IPU           (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->BSRR|= GPIO_Pin_0,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPA0_IPD           (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->BRR |= GPIO_Pin_0,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPA0_OUT_PP_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_10MHz(0))
#define configPA0_OUT_PP_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_2MHz(0))
#define configPA0_OUT_PP_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_50MHz(0))
#define configPA0_OUT_OD_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_10MHz(0))
#define configPA0_OUT_OD_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_2MHz(0))
#define configPA0_OUT_OD_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_50MHz(0))
#define configPA0_AF_PP_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_10MHz(0))
#define configPA0_AF_PP_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_2MHz(0))
#define configPA0_AF_PP_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_50MHz(0))
#define configPA0_AF_OD_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_10MHz(0))
#define configPA0_AF_OD_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_2MHz(0))
#define configPA0_AF_OD_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_50MHz(0))


/*******************************  PA1 configuration define *******************************/
#define configPA1_AIN           (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_AIN(1))
#define configPA1_IN_FLOATING   (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_IN_FLOATING(1))
#define configPA1_IPU           (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->BSRR|= GPIO_Pin_1,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPA1_IPD           (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->BRR |= GPIO_Pin_1,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPA1_OUT_PP_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_10MHz(1))
#define configPA1_OUT_PP_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_2MHz(1))
#define configPA1_OUT_PP_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_50MHz(1))
#define configPA1_OUT_OD_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_10MHz(1))
#define configPA1_OUT_OD_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_2MHz(1))
#define configPA1_OUT_OD_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_50MHz(1))
#define configPA1_AF_PP_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_10MHz(1))
#define configPA1_AF_PP_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_2MHz(1))
#define configPA1_AF_PP_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_50MHz(1))
#define configPA1_AF_OD_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_10MHz(1))
#define configPA1_AF_OD_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_2MHz(1))
#define configPA1_AF_OD_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_50MHz(1))


/*******************************  PA2 configuration define *******************************/
#define configPA2_AIN           (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_AIN(2))
#define configPA2_IN_FLOATING   (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_IN_FLOATING(2))
#define configPA2_IPU           (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->BSRR|= GPIO_Pin_2,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPA2_IPD           (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->BRR |= GPIO_Pin_2,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPA2_OUT_PP_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_10MHz(2))
#define configPA2_OUT_PP_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_2MHz(2))
#define configPA2_OUT_PP_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_50MHz(2))
#define configPA2_OUT_OD_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_10MHz(2))
#define configPA2_OUT_OD_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_2MHz(2))
#define configPA2_OUT_OD_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_50MHz(2))
#define configPA2_AF_PP_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_10MHz(2))
#define configPA2_AF_PP_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_2MHz(2))
#define configPA2_AF_PP_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_50MHz(2))
#define configPA2_AF_OD_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_10MHz(2))
#define configPA2_AF_OD_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_2MHz(2))
#define configPA2_AF_OD_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_50MHz(2))


/*******************************  PA3 configuration define *******************************/
#define configPA3_AIN           (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_AIN(3))
#define configPA3_IN_FLOATING   (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_IN_FLOATING(3))
#define configPA3_IPU           (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->BSRR|= GPIO_Pin_3,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPA3_IPD           (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->BRR |= GPIO_Pin_3,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPA3_OUT_PP_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_10MHz(3))
#define configPA3_OUT_PP_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_2MHz(3))
#define configPA3_OUT_PP_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_50MHz(3))
#define configPA3_OUT_OD_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_10MHz(3))
#define configPA3_OUT_OD_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_2MHz(3))
#define configPA3_OUT_OD_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_50MHz(3))
#define configPA3_AF_PP_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_10MHz(3))
#define configPA3_AF_PP_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_2MHz(3))
#define configPA3_AF_PP_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_50MHz(3))
#define configPA3_AF_OD_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_10MHz(3))
#define configPA3_AF_OD_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_2MHz(3))
#define configPA3_AF_OD_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_50MHz(3))


/*******************************  PA4 configuration define *******************************/
#define configPA4_AIN           (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_AIN(4))
#define configPA4_IN_FLOATING   (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_IN_FLOATING(4))
#define configPA4_IPU           (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->BSRR|= GPIO_Pin_4,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPA4_IPD           (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->BRR |= GPIO_Pin_4,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPA4_OUT_PP_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_10MHz(4))
#define configPA4_OUT_PP_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_2MHz(4))
#define configPA4_OUT_PP_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_50MHz(4))
#define configPA4_OUT_OD_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_10MHz(4))
#define configPA4_OUT_OD_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_2MHz(4))
#define configPA4_OUT_OD_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_50MHz(4))
#define configPA4_AF_PP_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_10MHz(4))
#define configPA4_AF_PP_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_2MHz(4))
#define configPA4_AF_PP_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_50MHz(4))
#define configPA4_AF_OD_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_10MHz(4))
#define configPA4_AF_OD_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_2MHz(4))
#define configPA4_AF_OD_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_50MHz(4))


/*******************************  PA5 configuration define *******************************/
#define configPA5_AIN           (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_AIN(5))
#define configPA5_IN_FLOATING   (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_IN_FLOATING(5))
#define configPA5_IPU           (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->BSRR|= GPIO_Pin_5,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPA5_IPD           (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->BRR |= GPIO_Pin_5,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPA5_OUT_PP_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_10MHz(5))
#define configPA5_OUT_PP_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_2MHz(5))
#define configPA5_OUT_PP_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_50MHz(5))
#define configPA5_OUT_OD_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_10MHz(5))
#define configPA5_OUT_OD_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_2MHz(5))
#define configPA5_OUT_OD_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_50MHz(5))
#define configPA5_AF_PP_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_10MHz(5))
#define configPA5_AF_PP_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_2MHz(5))
#define configPA5_AF_PP_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_50MHz(5))
#define configPA5_AF_OD_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_10MHz(5))
#define configPA5_AF_OD_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_2MHz(5))
#define configPA5_AF_OD_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_50MHz(5))


/*******************************  PA6 configuration define *******************************/
#define configPA6_AIN           (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_AIN(6))
#define configPA6_IN_FLOATING   (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_IN_FLOATING(6))
#define configPA6_IPU           (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->BSRR|= GPIO_Pin_6,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPA6_IPD           (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->BRR |= GPIO_Pin_6,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPA6_OUT_PP_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_10MHz(6))
#define configPA6_OUT_PP_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_2MHz(6))
#define configPA6_OUT_PP_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_50MHz(6))
#define configPA6_OUT_OD_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_10MHz(6))
#define configPA6_OUT_OD_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_2MHz(6))
#define configPA6_OUT_OD_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_50MHz(6))
#define configPA6_AF_PP_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_10MHz(6))
#define configPA6_AF_PP_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_2MHz(6))
#define configPA6_AF_PP_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_50MHz(6))
#define configPA6_AF_OD_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_10MHz(6))
#define configPA6_AF_OD_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_2MHz(6))
#define configPA6_AF_OD_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_50MHz(6))


/*******************************  PA7 configuration define *******************************/
#define configPA7_AIN           (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_AIN(7))
#define configPA7_IN_FLOATING   (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_IN_FLOATING(7))
#define configPA7_IPU           (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->BSRR|= GPIO_Pin_7,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPA7_IPD           (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->BRR |= GPIO_Pin_7,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPA7_OUT_PP_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_10MHz(7))
#define configPA7_OUT_PP_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_2MHz(7))
#define configPA7_OUT_PP_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_50MHz(7))
#define configPA7_OUT_OD_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_10MHz(7))
#define configPA7_OUT_OD_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_2MHz(7))
#define configPA7_OUT_OD_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_50MHz(7))
#define configPA7_AF_PP_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_10MHz(7))
#define configPA7_AF_PP_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_2MHz(7))
#define configPA7_AF_PP_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_50MHz(7))
#define configPA7_AF_OD_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_10MHz(7))
#define configPA7_AF_OD_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_2MHz(7))
#define configPA7_AF_OD_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_50MHz(7))


/*******************************  PA8 configuration define *******************************/
#define configPA8_AIN           (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_AIN(8))
#define configPA8_IN_FLOATING   (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_IN_FLOATING(8))
#define configPA8_IPU           (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->BSRR|= GPIO_Pin_8,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPA8_IPD           (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->BRR |= GPIO_Pin_8,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPA8_OUT_PP_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_10MHz(8))
#define configPA8_OUT_PP_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_2MHz(8))
#define configPA8_OUT_PP_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_50MHz(8))
#define configPA8_OUT_OD_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_10MHz(8))
#define configPA8_OUT_OD_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_2MHz(8))
#define configPA8_OUT_OD_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_50MHz(8))
#define configPA8_AF_PP_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_10MHz(8))
#define configPA8_AF_PP_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_2MHz(8))
#define configPA8_AF_PP_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_50MHz(8))
#define configPA8_AF_OD_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_10MHz(8))
#define configPA8_AF_OD_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_2MHz(8))
#define configPA8_AF_OD_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_50MHz(8))


/*******************************  PA9 configuration define *******************************/
#define configPA9_AIN           (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_AIN(9))
#define configPA9_IN_FLOATING   (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_IN_FLOATING(9))
#define configPA9_IPU           (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->BSRR|= GPIO_Pin_9,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPA9_IPD           (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->BRR |= GPIO_Pin_9,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPA9_OUT_PP_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_10MHz(9))
#define configPA9_OUT_PP_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_2MHz(9))
#define configPA9_OUT_PP_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_50MHz(9))
#define configPA9_OUT_OD_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_10MHz(9))
#define configPA9_OUT_OD_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_2MHz(9))
#define configPA9_OUT_OD_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_50MHz(9))
#define configPA9_AF_PP_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_10MHz(9))
#define configPA9_AF_PP_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_2MHz(9))
#define configPA9_AF_PP_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_50MHz(9))
#define configPA9_AF_OD_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_10MHz(9))
#define configPA9_AF_OD_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_2MHz(9))
#define configPA9_AF_OD_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_50MHz(9))


/*******************************  PA10 configuration define *******************************/
#define configPA10_AIN           (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_AIN(10))
#define configPA10_IN_FLOATING   (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_IN_FLOATING(10))
#define configPA10_IPU           (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->BSRR|= GPIO_Pin_10,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPA10_IPD           (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->BRR |= GPIO_Pin_10,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPA10_OUT_PP_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_10MHz(10))
#define configPA10_OUT_PP_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_2MHz(10))
#define configPA10_OUT_PP_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_50MHz(10))
#define configPA10_OUT_OD_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_10MHz(10))
#define configPA10_OUT_OD_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_2MHz(10))
#define configPA10_OUT_OD_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_50MHz(10))
#define configPA10_AF_PP_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_10MHz(10))
#define configPA10_AF_PP_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_2MHz(10))
#define configPA10_AF_PP_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_50MHz(10))
#define configPA10_AF_OD_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_10MHz(10))
#define configPA10_AF_OD_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_2MHz(10))
#define configPA10_AF_OD_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_50MHz(10))


/*******************************  PA11 configuration define *******************************/
#define configPA11_AIN           (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_AIN(11))
#define configPA11_IN_FLOATING   (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_IN_FLOATING(11))
#define configPA11_IPU           (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->BSRR|= GPIO_Pin_11,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPA11_IPD           (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->BRR |= GPIO_Pin_11,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPA11_OUT_PP_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_10MHz(11))
#define configPA11_OUT_PP_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_2MHz(11))
#define configPA11_OUT_PP_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_50MHz(11))
#define configPA11_OUT_OD_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_10MHz(11))
#define configPA11_OUT_OD_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_2MHz(11))
#define configPA11_OUT_OD_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_50MHz(11))
#define configPA11_AF_PP_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_10MHz(11))
#define configPA11_AF_PP_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_2MHz(11))
#define configPA11_AF_PP_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_50MHz(11))
#define configPA11_AF_OD_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_10MHz(11))
#define configPA11_AF_OD_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_2MHz(11))
#define configPA11_AF_OD_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_50MHz(11))


/*******************************  PA12 configuration define *******************************/
#define configPA12_AIN           (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_AIN(12))
#define configPA12_IN_FLOATING   (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_IN_FLOATING(12))
#define configPA12_IPU           (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->BSRR|= GPIO_Pin_12,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPA12_IPD           (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->BRR |= GPIO_Pin_12,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPA12_OUT_PP_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_10MHz(12))
#define configPA12_OUT_PP_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_2MHz(12))
#define configPA12_OUT_PP_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_50MHz(12))
#define configPA12_OUT_OD_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_10MHz(12))
#define configPA12_OUT_OD_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_2MHz(12))
#define configPA12_OUT_OD_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_50MHz(12))
#define configPA12_AF_PP_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_10MHz(12))
#define configPA12_AF_PP_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_2MHz(12))
#define configPA12_AF_PP_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_50MHz(12))
#define configPA12_AF_OD_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_10MHz(12))
#define configPA12_AF_OD_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_2MHz(12))
#define configPA12_AF_OD_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_50MHz(12))


/*******************************  PA13 configuration define *******************************/
#define configPA13_AIN           (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_AIN(13))
#define configPA13_IN_FLOATING   (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_IN_FLOATING(13))
#define configPA13_IPU           (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->BSRR|= GPIO_Pin_13,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPA13_IPD           (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->BRR |= GPIO_Pin_13,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPA13_OUT_PP_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_10MHz(13))
#define configPA13_OUT_PP_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_2MHz(13))
#define configPA13_OUT_PP_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_50MHz(13))
#define configPA13_OUT_OD_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_10MHz(13))
#define configPA13_OUT_OD_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_2MHz(13))
#define configPA13_OUT_OD_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_50MHz(13))
#define configPA13_AF_PP_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_10MHz(13))
#define configPA13_AF_PP_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_2MHz(13))
#define configPA13_AF_PP_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_50MHz(13))
#define configPA13_AF_OD_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_10MHz(13))
#define configPA13_AF_OD_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_2MHz(13))
#define configPA13_AF_OD_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_50MHz(13))


/*******************************  PA14 configuration define *******************************/
#define configPA14_AIN           (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_AIN(14))
#define configPA14_IN_FLOATING   (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_IN_FLOATING(14))
#define configPA14_IPU           (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->BSRR|= GPIO_Pin_14,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPA14_IPD           (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->BRR |= GPIO_Pin_14,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPA14_OUT_PP_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_10MHz(14))
#define configPA14_OUT_PP_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_2MHz(14))
#define configPA14_OUT_PP_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_50MHz(14))
#define configPA14_OUT_OD_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_10MHz(14))
#define configPA14_OUT_OD_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_2MHz(14))
#define configPA14_OUT_OD_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_50MHz(14))
#define configPA14_AF_PP_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_10MHz(14))
#define configPA14_AF_PP_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_2MHz(14))
#define configPA14_AF_PP_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_50MHz(14))
#define configPA14_AF_OD_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_10MHz(14))
#define configPA14_AF_OD_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_2MHz(14))
#define configPA14_AF_OD_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_50MHz(14))


/*******************************  PA15 configuration define *******************************/
#define configPA15_AIN           (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_AIN(15))
#define configPA15_IN_FLOATING   (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_IN_FLOATING(15))
#define configPA15_IPU           (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->BSRR|= GPIO_Pin_15,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPA15_IPD           (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->BRR |= GPIO_Pin_15,  GPIOA->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPA15_OUT_PP_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_10MHz(15))
#define configPA15_OUT_PP_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_2MHz(15))
#define configPA15_OUT_PP_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_OUT_PP_50MHz(15))
#define configPA15_OUT_OD_10MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_10MHz(15))
#define configPA15_OUT_OD_2MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_2MHz(15))
#define configPA15_OUT_OD_50MHz  (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_OUT_OD_50MHz(15))
#define configPA15_AF_PP_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_10MHz(15))
#define configPA15_AF_PP_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_2MHz(15))
#define configPA15_AF_PP_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_AF_PP_50MHz(15))
#define configPA15_AF_OD_10MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_10MHz(15))
#define configPA15_AF_OD_2MHz    (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_2MHz(15))
#define configPA15_AF_OD_50MHz   (GPIOA->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOA->CRH |= PIN_CONFIG_AF_OD_50MHz(15))


/*******************************  PB0 configuration define *******************************/
#define configPB0_AIN           (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_AIN(0))
#define configPB0_IN_FLOATING   (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_IN_FLOATING(0))
#define configPB0_IPU           (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->BSRR|= GPIO_Pin_0,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPB0_IPD           (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->BRR |= GPIO_Pin_0,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPB0_OUT_PP_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_10MHz(0))
#define configPB0_OUT_PP_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_2MHz(0))
#define configPB0_OUT_PP_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_50MHz(0))
#define configPB0_OUT_OD_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_10MHz(0))
#define configPB0_OUT_OD_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_2MHz(0))
#define configPB0_OUT_OD_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_50MHz(0))
#define configPB0_AF_PP_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_10MHz(0))
#define configPB0_AF_PP_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_2MHz(0))
#define configPB0_AF_PP_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_50MHz(0))
#define configPB0_AF_OD_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_10MHz(0))
#define configPB0_AF_OD_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_2MHz(0))
#define configPB0_AF_OD_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_50MHz(0))


/*******************************  PB1 configuration define *******************************/
#define configPB1_AIN           (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_AIN(1))
#define configPB1_IN_FLOATING   (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_IN_FLOATING(1))
#define configPB1_IPU           (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->BSRR|= GPIO_Pin_1,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPB1_IPD           (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->BRR |= GPIO_Pin_1,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPB1_OUT_PP_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_10MHz(1))
#define configPB1_OUT_PP_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_2MHz(1))
#define configPB1_OUT_PP_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_50MHz(1))
#define configPB1_OUT_OD_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_10MHz(1))
#define configPB1_OUT_OD_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_2MHz(1))
#define configPB1_OUT_OD_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_50MHz(1))
#define configPB1_AF_PP_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_10MHz(1))
#define configPB1_AF_PP_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_2MHz(1))
#define configPB1_AF_PP_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_50MHz(1))
#define configPB1_AF_OD_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_10MHz(1))
#define configPB1_AF_OD_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_2MHz(1))
#define configPB1_AF_OD_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_50MHz(1))


/*******************************  PB2 configuration define *******************************/
#define configPB2_AIN           (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_AIN(2))
#define configPB2_IN_FLOATING   (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_IN_FLOATING(2))
#define configPB2_IPU           (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->BSRR|= GPIO_Pin_2,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPB2_IPD           (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->BRR |= GPIO_Pin_2,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPB2_OUT_PP_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_10MHz(2))
#define configPB2_OUT_PP_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_2MHz(2))
#define configPB2_OUT_PP_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_50MHz(2))
#define configPB2_OUT_OD_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_10MHz(2))
#define configPB2_OUT_OD_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_2MHz(2))
#define configPB2_OUT_OD_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_50MHz(2))
#define configPB2_AF_PP_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_10MHz(2))
#define configPB2_AF_PP_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_2MHz(2))
#define configPB2_AF_PP_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_50MHz(2))
#define configPB2_AF_OD_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_10MHz(2))
#define configPB2_AF_OD_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_2MHz(2))
#define configPB2_AF_OD_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_50MHz(2))


/*******************************  PB3 configuration define *******************************/
#define configPB3_AIN           (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_AIN(3))
#define configPB3_IN_FLOATING   (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_IN_FLOATING(3))
#define configPB3_IPU           (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->BSRR|= GPIO_Pin_3,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPB3_IPD           (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->BRR |= GPIO_Pin_3,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPB3_OUT_PP_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_10MHz(3))
#define configPB3_OUT_PP_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_2MHz(3))
#define configPB3_OUT_PP_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_50MHz(3))
#define configPB3_OUT_OD_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_10MHz(3))
#define configPB3_OUT_OD_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_2MHz(3))
#define configPB3_OUT_OD_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_50MHz(3))
#define configPB3_AF_PP_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_10MHz(3))
#define configPB3_AF_PP_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_2MHz(3))
#define configPB3_AF_PP_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_50MHz(3))
#define configPB3_AF_OD_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_10MHz(3))
#define configPB3_AF_OD_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_2MHz(3))
#define configPB3_AF_OD_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_50MHz(3))


/*******************************  PB4 configuration define *******************************/
#define configPB4_AIN           (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_AIN(4))
#define configPB4_IN_FLOATING   (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_IN_FLOATING(4))
#define configPB4_IPU           (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->BSRR|= GPIO_Pin_4,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPB4_IPD           (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->BRR |= GPIO_Pin_4,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPB4_OUT_PP_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_10MHz(4))
#define configPB4_OUT_PP_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_2MHz(4))
#define configPB4_OUT_PP_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_50MHz(4))
#define configPB4_OUT_OD_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_10MHz(4))
#define configPB4_OUT_OD_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_2MHz(4))
#define configPB4_OUT_OD_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_50MHz(4))
#define configPB4_AF_PP_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_10MHz(4))
#define configPB4_AF_PP_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_2MHz(4))
#define configPB4_AF_PP_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_50MHz(4))
#define configPB4_AF_OD_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_10MHz(4))
#define configPB4_AF_OD_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_2MHz(4))
#define configPB4_AF_OD_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_50MHz(4))


/*******************************  PB5 configuration define *******************************/
#define configPB5_AIN           (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_AIN(5))
#define configPB5_IN_FLOATING   (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_IN_FLOATING(5))
#define configPB5_IPU           (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->BSRR|= GPIO_Pin_5,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPB5_IPD           (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->BRR |= GPIO_Pin_5,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPB5_OUT_PP_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_10MHz(5))
#define configPB5_OUT_PP_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_2MHz(5))
#define configPB5_OUT_PP_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_50MHz(5))
#define configPB5_OUT_OD_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_10MHz(5))
#define configPB5_OUT_OD_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_2MHz(5))
#define configPB5_OUT_OD_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_50MHz(5))
#define configPB5_AF_PP_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_10MHz(5))
#define configPB5_AF_PP_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_2MHz(5))
#define configPB5_AF_PP_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_50MHz(5))
#define configPB5_AF_OD_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_10MHz(5))
#define configPB5_AF_OD_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_2MHz(5))
#define configPB5_AF_OD_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_50MHz(5))


/*******************************  PB6 configuration define *******************************/
#define configPB6_AIN           (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_AIN(6))
#define configPB6_IN_FLOATING   (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_IN_FLOATING(6))
#define configPB6_IPU           (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->BSRR|= GPIO_Pin_6,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPB6_IPD           (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->BRR |= GPIO_Pin_6,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPB6_OUT_PP_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_10MHz(6))
#define configPB6_OUT_PP_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_2MHz(6))
#define configPB6_OUT_PP_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_50MHz(6))
#define configPB6_OUT_OD_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_10MHz(6))
#define configPB6_OUT_OD_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_2MHz(6))
#define configPB6_OUT_OD_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_50MHz(6))
#define configPB6_AF_PP_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_10MHz(6))
#define configPB6_AF_PP_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_2MHz(6))
#define configPB6_AF_PP_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_50MHz(6))
#define configPB6_AF_OD_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_10MHz(6))
#define configPB6_AF_OD_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_2MHz(6))
#define configPB6_AF_OD_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_50MHz(6))


/*******************************  PB7 configuration define *******************************/
#define configPB7_AIN           (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_AIN(7))
#define configPB7_IN_FLOATING   (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_IN_FLOATING(7))
#define configPB7_IPU           (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->BSRR|= GPIO_Pin_7,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPB7_IPD           (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->BRR |= GPIO_Pin_7,  GPIOB->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPB7_OUT_PP_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_10MHz(7))
#define configPB7_OUT_PP_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_2MHz(7))
#define configPB7_OUT_PP_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_OUT_PP_50MHz(7))
#define configPB7_OUT_OD_10MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_10MHz(7))
#define configPB7_OUT_OD_2MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_2MHz(7))
#define configPB7_OUT_OD_50MHz  (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_OUT_OD_50MHz(7))
#define configPB7_AF_PP_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_10MHz(7))
#define configPB7_AF_PP_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_2MHz(7))
#define configPB7_AF_PP_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_AF_PP_50MHz(7))
#define configPB7_AF_OD_10MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_10MHz(7))
#define configPB7_AF_OD_2MHz    (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_2MHz(7))
#define configPB7_AF_OD_50MHz   (GPIOB->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOB->CRL |= PIN_CONFIG_AF_OD_50MHz(7))


/*******************************  PB8 configuration define *******************************/
#define configPB8_AIN           (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_AIN(8))
#define configPB8_IN_FLOATING   (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_IN_FLOATING(8))
#define configPB8_IPU           (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->BSRR|= GPIO_Pin_8,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPB8_IPD           (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->BRR |= GPIO_Pin_8,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPB8_OUT_PP_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_10MHz(8))
#define configPB8_OUT_PP_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_2MHz(8))
#define configPB8_OUT_PP_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_50MHz(8))
#define configPB8_OUT_OD_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_10MHz(8))
#define configPB8_OUT_OD_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_2MHz(8))
#define configPB8_OUT_OD_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_50MHz(8))
#define configPB8_AF_PP_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_10MHz(8))
#define configPB8_AF_PP_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_2MHz(8))
#define configPB8_AF_PP_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_50MHz(8))
#define configPB8_AF_OD_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_10MHz(8))
#define configPB8_AF_OD_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_2MHz(8))
#define configPB8_AF_OD_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_50MHz(8))


/*******************************  PB9 configuration define *******************************/
#define configPB9_AIN           (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_AIN(9))
#define configPB9_IN_FLOATING   (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_IN_FLOATING(9))
#define configPB9_IPU           (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->BSRR|= GPIO_Pin_9,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPB9_IPD           (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->BRR |= GPIO_Pin_9,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPB9_OUT_PP_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_10MHz(9))
#define configPB9_OUT_PP_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_2MHz(9))
#define configPB9_OUT_PP_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_50MHz(9))
#define configPB9_OUT_OD_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_10MHz(9))
#define configPB9_OUT_OD_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_2MHz(9))
#define configPB9_OUT_OD_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_50MHz(9))
#define configPB9_AF_PP_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_10MHz(9))
#define configPB9_AF_PP_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_2MHz(9))
#define configPB9_AF_PP_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_50MHz(9))
#define configPB9_AF_OD_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_10MHz(9))
#define configPB9_AF_OD_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_2MHz(9))
#define configPB9_AF_OD_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_50MHz(9))


/*******************************  PB10 configuration define *******************************/
#define configPB10_AIN           (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_AIN(10))
#define configPB10_IN_FLOATING   (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_IN_FLOATING(10))
#define configPB10_IPU           (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->BSRR|= GPIO_Pin_10,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPB10_IPD           (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->BRR |= GPIO_Pin_10,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPB10_OUT_PP_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_10MHz(10))
#define configPB10_OUT_PP_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_2MHz(10))
#define configPB10_OUT_PP_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_50MHz(10))
#define configPB10_OUT_OD_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_10MHz(10))
#define configPB10_OUT_OD_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_2MHz(10))
#define configPB10_OUT_OD_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_50MHz(10))
#define configPB10_AF_PP_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_10MHz(10))
#define configPB10_AF_PP_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_2MHz(10))
#define configPB10_AF_PP_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_50MHz(10))
#define configPB10_AF_OD_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_10MHz(10))
#define configPB10_AF_OD_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_2MHz(10))
#define configPB10_AF_OD_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_50MHz(10))


/*******************************  PB11 configuration define *******************************/
#define configPB11_AIN           (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_AIN(11))
#define configPB11_IN_FLOATING   (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_IN_FLOATING(11))
#define configPB11_IPU           (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->BSRR|= GPIO_Pin_11,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPB11_IPD           (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->BRR |= GPIO_Pin_11,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPB11_OUT_PP_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_10MHz(11))
#define configPB11_OUT_PP_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_2MHz(11))
#define configPB11_OUT_PP_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_50MHz(11))
#define configPB11_OUT_OD_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_10MHz(11))
#define configPB11_OUT_OD_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_2MHz(11))
#define configPB11_OUT_OD_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_50MHz(11))
#define configPB11_AF_PP_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_10MHz(11))
#define configPB11_AF_PP_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_2MHz(11))
#define configPB11_AF_PP_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_50MHz(11))
#define configPB11_AF_OD_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_10MHz(11))
#define configPB11_AF_OD_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_2MHz(11))
#define configPB11_AF_OD_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_50MHz(11))


/*******************************  PB12 configuration define *******************************/
#define configPB12_AIN           (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_AIN(12))
#define configPB12_IN_FLOATING   (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_IN_FLOATING(12))
#define configPB12_IPU           (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->BSRR|= GPIO_Pin_12,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPB12_IPD           (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->BRR |= GPIO_Pin_12,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPB12_OUT_PP_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_10MHz(12))
#define configPB12_OUT_PP_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_2MHz(12))
#define configPB12_OUT_PP_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_50MHz(12))
#define configPB12_OUT_OD_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_10MHz(12))
#define configPB12_OUT_OD_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_2MHz(12))
#define configPB12_OUT_OD_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_50MHz(12))
#define configPB12_AF_PP_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_10MHz(12))
#define configPB12_AF_PP_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_2MHz(12))
#define configPB12_AF_PP_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_50MHz(12))
#define configPB12_AF_OD_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_10MHz(12))
#define configPB12_AF_OD_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_2MHz(12))
#define configPB12_AF_OD_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_50MHz(12))


/*******************************  PB13 configuration define *******************************/
#define configPB13_AIN           (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_AIN(13))
#define configPB13_IN_FLOATING   (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_IN_FLOATING(13))
#define configPB13_IPU           (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->BSRR|= GPIO_Pin_13,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPB13_IPD           (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->BRR |= GPIO_Pin_13,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPB13_OUT_PP_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_10MHz(13))
#define configPB13_OUT_PP_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_2MHz(13))
#define configPB13_OUT_PP_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_50MHz(13))
#define configPB13_OUT_OD_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_10MHz(13))
#define configPB13_OUT_OD_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_2MHz(13))
#define configPB13_OUT_OD_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_50MHz(13))
#define configPB13_AF_PP_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_10MHz(13))
#define configPB13_AF_PP_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_2MHz(13))
#define configPB13_AF_PP_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_50MHz(13))
#define configPB13_AF_OD_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_10MHz(13))
#define configPB13_AF_OD_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_2MHz(13))
#define configPB13_AF_OD_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_50MHz(13))


/*******************************  PB14 configuration define *******************************/
#define configPB14_AIN           (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_AIN(14))
#define configPB14_IN_FLOATING   (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_IN_FLOATING(14))
#define configPB14_IPU           (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->BSRR|= GPIO_Pin_14,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPB14_IPD           (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->BRR |= GPIO_Pin_14,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPB14_OUT_PP_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_10MHz(14))
#define configPB14_OUT_PP_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_2MHz(14))
#define configPB14_OUT_PP_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_50MHz(14))
#define configPB14_OUT_OD_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_10MHz(14))
#define configPB14_OUT_OD_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_2MHz(14))
#define configPB14_OUT_OD_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_50MHz(14))
#define configPB14_AF_PP_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_10MHz(14))
#define configPB14_AF_PP_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_2MHz(14))
#define configPB14_AF_PP_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_50MHz(14))
#define configPB14_AF_OD_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_10MHz(14))
#define configPB14_AF_OD_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_2MHz(14))
#define configPB14_AF_OD_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_50MHz(14))


/*******************************  PB15 configuration define *******************************/
#define configPB15_AIN           (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_AIN(15))
#define configPB15_IN_FLOATING   (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_IN_FLOATING(15))
#define configPB15_IPU           (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->BSRR|= GPIO_Pin_15,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPB15_IPD           (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->BRR |= GPIO_Pin_15,  GPIOB->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPB15_OUT_PP_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_10MHz(15))
#define configPB15_OUT_PP_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_2MHz(15))
#define configPB15_OUT_PP_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_OUT_PP_50MHz(15))
#define configPB15_OUT_OD_10MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_10MHz(15))
#define configPB15_OUT_OD_2MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_2MHz(15))
#define configPB15_OUT_OD_50MHz  (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_OUT_OD_50MHz(15))
#define configPB15_AF_PP_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_10MHz(15))
#define configPB15_AF_PP_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_2MHz(15))
#define configPB15_AF_PP_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_AF_PP_50MHz(15))
#define configPB15_AF_OD_10MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_10MHz(15))
#define configPB15_AF_OD_2MHz    (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_2MHz(15))
#define configPB15_AF_OD_50MHz   (GPIOB->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOB->CRH |= PIN_CONFIG_AF_OD_50MHz(15))


/*******************************  PC0 configuration define *******************************/
#define configPC0_AIN           (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_AIN(0))
#define configPC0_IN_FLOATING   (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_IN_FLOATING(0))
#define configPC0_IPU           (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->BSRR|= GPIO_Pin_0,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPC0_IPD           (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->BRR |= GPIO_Pin_0,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPC0_OUT_PP_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_10MHz(0))
#define configPC0_OUT_PP_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_2MHz(0))
#define configPC0_OUT_PP_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_50MHz(0))
#define configPC0_OUT_OD_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_10MHz(0))
#define configPC0_OUT_OD_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_2MHz(0))
#define configPC0_OUT_OD_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_50MHz(0))
#define configPC0_AF_PP_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_10MHz(0))
#define configPC0_AF_PP_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_2MHz(0))
#define configPC0_AF_PP_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_50MHz(0))
#define configPC0_AF_OD_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_10MHz(0))
#define configPC0_AF_OD_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_2MHz(0))
#define configPC0_AF_OD_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_50MHz(0))


/*******************************  PC1 configuration define *******************************/
#define configPC1_AIN           (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_AIN(1))
#define configPC1_IN_FLOATING   (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_IN_FLOATING(1))
#define configPC1_IPU           (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->BSRR|= GPIO_Pin_1,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPC1_IPD           (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->BRR |= GPIO_Pin_1,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPC1_OUT_PP_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_10MHz(1))
#define configPC1_OUT_PP_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_2MHz(1))
#define configPC1_OUT_PP_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_50MHz(1))
#define configPC1_OUT_OD_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_10MHz(1))
#define configPC1_OUT_OD_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_2MHz(1))
#define configPC1_OUT_OD_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_50MHz(1))
#define configPC1_AF_PP_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_10MHz(1))
#define configPC1_AF_PP_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_2MHz(1))
#define configPC1_AF_PP_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_50MHz(1))
#define configPC1_AF_OD_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_10MHz(1))
#define configPC1_AF_OD_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_2MHz(1))
#define configPC1_AF_OD_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_50MHz(1))


/*******************************  PC2 configuration define *******************************/
#define configPC2_AIN           (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_AIN(2))
#define configPC2_IN_FLOATING   (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_IN_FLOATING(2))
#define configPC2_IPU           (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->BSRR|= GPIO_Pin_2,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPC2_IPD           (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->BRR |= GPIO_Pin_2,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPC2_OUT_PP_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_10MHz(2))
#define configPC2_OUT_PP_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_2MHz(2))
#define configPC2_OUT_PP_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_50MHz(2))
#define configPC2_OUT_OD_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_10MHz(2))
#define configPC2_OUT_OD_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_2MHz(2))
#define configPC2_OUT_OD_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_50MHz(2))
#define configPC2_AF_PP_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_10MHz(2))
#define configPC2_AF_PP_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_2MHz(2))
#define configPC2_AF_PP_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_50MHz(2))
#define configPC2_AF_OD_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_10MHz(2))
#define configPC2_AF_OD_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_2MHz(2))
#define configPC2_AF_OD_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_50MHz(2))


/*******************************  PC3 configuration define *******************************/
#define configPC3_AIN           (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_AIN(3))
#define configPC3_IN_FLOATING   (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_IN_FLOATING(3))
#define configPC3_IPU           (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->BSRR|= GPIO_Pin_3,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPC3_IPD           (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->BRR |= GPIO_Pin_3,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPC3_OUT_PP_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_10MHz(3))
#define configPC3_OUT_PP_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_2MHz(3))
#define configPC3_OUT_PP_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_50MHz(3))
#define configPC3_OUT_OD_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_10MHz(3))
#define configPC3_OUT_OD_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_2MHz(3))
#define configPC3_OUT_OD_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_50MHz(3))
#define configPC3_AF_PP_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_10MHz(3))
#define configPC3_AF_PP_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_2MHz(3))
#define configPC3_AF_PP_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_50MHz(3))
#define configPC3_AF_OD_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_10MHz(3))
#define configPC3_AF_OD_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_2MHz(3))
#define configPC3_AF_OD_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_50MHz(3))


/*******************************  PC4 configuration define *******************************/
#define configPC4_AIN           (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_AIN(4))
#define configPC4_IN_FLOATING   (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_IN_FLOATING(4))
#define configPC4_IPU           (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->BSRR|= GPIO_Pin_4,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPC4_IPD           (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->BRR |= GPIO_Pin_4,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPC4_OUT_PP_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_10MHz(4))
#define configPC4_OUT_PP_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_2MHz(4))
#define configPC4_OUT_PP_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_50MHz(4))
#define configPC4_OUT_OD_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_10MHz(4))
#define configPC4_OUT_OD_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_2MHz(4))
#define configPC4_OUT_OD_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_50MHz(4))
#define configPC4_AF_PP_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_10MHz(4))
#define configPC4_AF_PP_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_2MHz(4))
#define configPC4_AF_PP_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_50MHz(4))
#define configPC4_AF_OD_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_10MHz(4))
#define configPC4_AF_OD_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_2MHz(4))
#define configPC4_AF_OD_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_50MHz(4))


/*******************************  PC5 configuration define *******************************/
#define configPC5_AIN           (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_AIN(5))
#define configPC5_IN_FLOATING   (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_IN_FLOATING(5))
#define configPC5_IPU           (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->BSRR|= GPIO_Pin_5,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPC5_IPD           (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->BRR |= GPIO_Pin_5,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPC5_OUT_PP_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_10MHz(5))
#define configPC5_OUT_PP_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_2MHz(5))
#define configPC5_OUT_PP_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_50MHz(5))
#define configPC5_OUT_OD_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_10MHz(5))
#define configPC5_OUT_OD_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_2MHz(5))
#define configPC5_OUT_OD_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_50MHz(5))
#define configPC5_AF_PP_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_10MHz(5))
#define configPC5_AF_PP_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_2MHz(5))
#define configPC5_AF_PP_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_50MHz(5))
#define configPC5_AF_OD_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_10MHz(5))
#define configPC5_AF_OD_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_2MHz(5))
#define configPC5_AF_OD_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_50MHz(5))


/*******************************  PC6 configuration define *******************************/
#define configPC6_AIN           (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_AIN(6))
#define configPC6_IN_FLOATING   (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_IN_FLOATING(6))
#define configPC6_IPU           (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->BSRR|= GPIO_Pin_6,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPC6_IPD           (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->BRR |= GPIO_Pin_6,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPC6_OUT_PP_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_10MHz(6))
#define configPC6_OUT_PP_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_2MHz(6))
#define configPC6_OUT_PP_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_50MHz(6))
#define configPC6_OUT_OD_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_10MHz(6))
#define configPC6_OUT_OD_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_2MHz(6))
#define configPC6_OUT_OD_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_50MHz(6))
#define configPC6_AF_PP_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_10MHz(6))
#define configPC6_AF_PP_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_2MHz(6))
#define configPC6_AF_PP_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_50MHz(6))
#define configPC6_AF_OD_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_10MHz(6))
#define configPC6_AF_OD_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_2MHz(6))
#define configPC6_AF_OD_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_50MHz(6))


/*******************************  PC7 configuration define *******************************/
#define configPC7_AIN           (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_AIN(7))
#define configPC7_IN_FLOATING   (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_IN_FLOATING(7))
#define configPC7_IPU           (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->BSRR|= GPIO_Pin_7,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPC7_IPD           (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->BRR |= GPIO_Pin_7,  GPIOC->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPC7_OUT_PP_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_10MHz(7))
#define configPC7_OUT_PP_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_2MHz(7))
#define configPC7_OUT_PP_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_OUT_PP_50MHz(7))
#define configPC7_OUT_OD_10MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_10MHz(7))
#define configPC7_OUT_OD_2MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_2MHz(7))
#define configPC7_OUT_OD_50MHz  (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_OUT_OD_50MHz(7))
#define configPC7_AF_PP_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_10MHz(7))
#define configPC7_AF_PP_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_2MHz(7))
#define configPC7_AF_PP_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_AF_PP_50MHz(7))
#define configPC7_AF_OD_10MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_10MHz(7))
#define configPC7_AF_OD_2MHz    (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_2MHz(7))
#define configPC7_AF_OD_50MHz   (GPIOC->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOC->CRL |= PIN_CONFIG_AF_OD_50MHz(7))


/*******************************  PC8 configuration define *******************************/
#define configPC8_AIN           (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_AIN(8))
#define configPC8_IN_FLOATING   (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_IN_FLOATING(8))
#define configPC8_IPU           (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->BSRR|= GPIO_Pin_8,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPC8_IPD           (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->BRR |= GPIO_Pin_8,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPC8_OUT_PP_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_10MHz(8))
#define configPC8_OUT_PP_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_2MHz(8))
#define configPC8_OUT_PP_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_50MHz(8))
#define configPC8_OUT_OD_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_10MHz(8))
#define configPC8_OUT_OD_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_2MHz(8))
#define configPC8_OUT_OD_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_50MHz(8))
#define configPC8_AF_PP_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_10MHz(8))
#define configPC8_AF_PP_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_2MHz(8))
#define configPC8_AF_PP_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_50MHz(8))
#define configPC8_AF_OD_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_10MHz(8))
#define configPC8_AF_OD_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_2MHz(8))
#define configPC8_AF_OD_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_50MHz(8))


/*******************************  PC9 configuration define *******************************/
#define configPC9_AIN           (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_AIN(9))
#define configPC9_IN_FLOATING   (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_IN_FLOATING(9))
#define configPC9_IPU           (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->BSRR|= GPIO_Pin_9,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPC9_IPD           (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->BRR |= GPIO_Pin_9,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPC9_OUT_PP_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_10MHz(9))
#define configPC9_OUT_PP_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_2MHz(9))
#define configPC9_OUT_PP_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_50MHz(9))
#define configPC9_OUT_OD_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_10MHz(9))
#define configPC9_OUT_OD_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_2MHz(9))
#define configPC9_OUT_OD_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_50MHz(9))
#define configPC9_AF_PP_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_10MHz(9))
#define configPC9_AF_PP_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_2MHz(9))
#define configPC9_AF_PP_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_50MHz(9))
#define configPC9_AF_OD_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_10MHz(9))
#define configPC9_AF_OD_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_2MHz(9))
#define configPC9_AF_OD_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_50MHz(9))


/*******************************  PC10 configuration define *******************************/
#define configPC10_AIN           (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_AIN(10))
#define configPC10_IN_FLOATING   (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_IN_FLOATING(10))
#define configPC10_IPU           (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->BSRR|= GPIO_Pin_10,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPC10_IPD           (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->BRR |= GPIO_Pin_10,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPC10_OUT_PP_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_10MHz(10))
#define configPC10_OUT_PP_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_2MHz(10))
#define configPC10_OUT_PP_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_50MHz(10))
#define configPC10_OUT_OD_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_10MHz(10))
#define configPC10_OUT_OD_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_2MHz(10))
#define configPC10_OUT_OD_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_50MHz(10))
#define configPC10_AF_PP_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_10MHz(10))
#define configPC10_AF_PP_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_2MHz(10))
#define configPC10_AF_PP_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_50MHz(10))
#define configPC10_AF_OD_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_10MHz(10))
#define configPC10_AF_OD_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_2MHz(10))
#define configPC10_AF_OD_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_50MHz(10))


/*******************************  PC11 configuration define *******************************/
#define configPC11_AIN           (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_AIN(11))
#define configPC11_IN_FLOATING   (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_IN_FLOATING(11))
#define configPC11_IPU           (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->BSRR|= GPIO_Pin_11,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPC11_IPD           (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->BRR |= GPIO_Pin_11,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPC11_OUT_PP_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_10MHz(11))
#define configPC11_OUT_PP_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_2MHz(11))
#define configPC11_OUT_PP_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_50MHz(11))
#define configPC11_OUT_OD_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_10MHz(11))
#define configPC11_OUT_OD_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_2MHz(11))
#define configPC11_OUT_OD_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_50MHz(11))
#define configPC11_AF_PP_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_10MHz(11))
#define configPC11_AF_PP_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_2MHz(11))
#define configPC11_AF_PP_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_50MHz(11))
#define configPC11_AF_OD_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_10MHz(11))
#define configPC11_AF_OD_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_2MHz(11))
#define configPC11_AF_OD_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_50MHz(11))


/*******************************  PC12 configuration define *******************************/
#define configPC12_AIN           (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_AIN(12))
#define configPC12_IN_FLOATING   (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_IN_FLOATING(12))
#define configPC12_IPU           (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->BSRR|= GPIO_Pin_12,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPC12_IPD           (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->BRR |= GPIO_Pin_12,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPC12_OUT_PP_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_10MHz(12))
#define configPC12_OUT_PP_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_2MHz(12))
#define configPC12_OUT_PP_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_50MHz(12))
#define configPC12_OUT_OD_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_10MHz(12))
#define configPC12_OUT_OD_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_2MHz(12))
#define configPC12_OUT_OD_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_50MHz(12))
#define configPC12_AF_PP_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_10MHz(12))
#define configPC12_AF_PP_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_2MHz(12))
#define configPC12_AF_PP_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_50MHz(12))
#define configPC12_AF_OD_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_10MHz(12))
#define configPC12_AF_OD_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_2MHz(12))
#define configPC12_AF_OD_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_50MHz(12))


/*******************************  PC13 configuration define *******************************/
#define configPC13_AIN           (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_AIN(13))
#define configPC13_IN_FLOATING   (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_IN_FLOATING(13))
#define configPC13_IPU           (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->BSRR|= GPIO_Pin_13,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPC13_IPD           (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->BRR |= GPIO_Pin_13,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPC13_OUT_PP_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_10MHz(13))
#define configPC13_OUT_PP_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_2MHz(13))
#define configPC13_OUT_PP_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_50MHz(13))
#define configPC13_OUT_OD_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_10MHz(13))
#define configPC13_OUT_OD_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_2MHz(13))
#define configPC13_OUT_OD_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_50MHz(13))
#define configPC13_AF_PP_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_10MHz(13))
#define configPC13_AF_PP_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_2MHz(13))
#define configPC13_AF_PP_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_50MHz(13))
#define configPC13_AF_OD_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_10MHz(13))
#define configPC13_AF_OD_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_2MHz(13))
#define configPC13_AF_OD_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_50MHz(13))


/*******************************  PC14 configuration define *******************************/
#define configPC14_AIN           (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_AIN(14))
#define configPC14_IN_FLOATING   (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_IN_FLOATING(14))
#define configPC14_IPU           (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->BSRR|= GPIO_Pin_14,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPC14_IPD           (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->BRR |= GPIO_Pin_14,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPC14_OUT_PP_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_10MHz(14))
#define configPC14_OUT_PP_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_2MHz(14))
#define configPC14_OUT_PP_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_50MHz(14))
#define configPC14_OUT_OD_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_10MHz(14))
#define configPC14_OUT_OD_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_2MHz(14))
#define configPC14_OUT_OD_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_50MHz(14))
#define configPC14_AF_PP_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_10MHz(14))
#define configPC14_AF_PP_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_2MHz(14))
#define configPC14_AF_PP_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_50MHz(14))
#define configPC14_AF_OD_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_10MHz(14))
#define configPC14_AF_OD_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_2MHz(14))
#define configPC14_AF_OD_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_50MHz(14))


/*******************************  PC15 configuration define *******************************/
#define configPC15_AIN           (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_AIN(15))
#define configPC15_IN_FLOATING   (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_IN_FLOATING(15))
#define configPC15_IPU           (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->BSRR|= GPIO_Pin_15,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPC15_IPD           (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->BRR |= GPIO_Pin_15,  GPIOC->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPC15_OUT_PP_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_10MHz(15))
#define configPC15_OUT_PP_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_2MHz(15))
#define configPC15_OUT_PP_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_OUT_PP_50MHz(15))
#define configPC15_OUT_OD_10MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_10MHz(15))
#define configPC15_OUT_OD_2MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_2MHz(15))
#define configPC15_OUT_OD_50MHz  (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_OUT_OD_50MHz(15))
#define configPC15_AF_PP_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_10MHz(15))
#define configPC15_AF_PP_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_2MHz(15))
#define configPC15_AF_PP_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_AF_PP_50MHz(15))
#define configPC15_AF_OD_10MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_10MHz(15))
#define configPC15_AF_OD_2MHz    (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_2MHz(15))
#define configPC15_AF_OD_50MHz   (GPIOC->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOC->CRH |= PIN_CONFIG_AF_OD_50MHz(15))


/*******************************  PD0 configuration define *******************************/
#define configPD0_AIN           (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_AIN(0))
#define configPD0_IN_FLOATING   (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_IN_FLOATING(0))
#define configPD0_IPU           (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->BSRR|= GPIO_Pin_0,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPD0_IPD           (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->BRR |= GPIO_Pin_0,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPD0_OUT_PP_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_10MHz(0))
#define configPD0_OUT_PP_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_2MHz(0))
#define configPD0_OUT_PP_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_50MHz(0))
#define configPD0_OUT_OD_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_10MHz(0))
#define configPD0_OUT_OD_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_2MHz(0))
#define configPD0_OUT_OD_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_50MHz(0))
#define configPD0_AF_PP_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_10MHz(0))
#define configPD0_AF_PP_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_2MHz(0))
#define configPD0_AF_PP_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_50MHz(0))
#define configPD0_AF_OD_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_10MHz(0))
#define configPD0_AF_OD_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_2MHz(0))
#define configPD0_AF_OD_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_50MHz(0))


/*******************************  PD1 configuration define *******************************/
#define configPD1_AIN           (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_AIN(1))
#define configPD1_IN_FLOATING   (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_IN_FLOATING(1))
#define configPD1_IPU           (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->BSRR|= GPIO_Pin_1,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPD1_IPD           (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->BRR |= GPIO_Pin_1,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPD1_OUT_PP_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_10MHz(1))
#define configPD1_OUT_PP_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_2MHz(1))
#define configPD1_OUT_PP_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_50MHz(1))
#define configPD1_OUT_OD_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_10MHz(1))
#define configPD1_OUT_OD_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_2MHz(1))
#define configPD1_OUT_OD_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_50MHz(1))
#define configPD1_AF_PP_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_10MHz(1))
#define configPD1_AF_PP_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_2MHz(1))
#define configPD1_AF_PP_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_50MHz(1))
#define configPD1_AF_OD_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_10MHz(1))
#define configPD1_AF_OD_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_2MHz(1))
#define configPD1_AF_OD_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_50MHz(1))


/*******************************  PD2 configuration define *******************************/
#define configPD2_AIN           (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_AIN(2))
#define configPD2_IN_FLOATING   (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_IN_FLOATING(2))
#define configPD2_IPU           (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->BSRR|= GPIO_Pin_2,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPD2_IPD           (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->BRR |= GPIO_Pin_2,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPD2_OUT_PP_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_10MHz(2))
#define configPD2_OUT_PP_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_2MHz(2))
#define configPD2_OUT_PP_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_50MHz(2))
#define configPD2_OUT_OD_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_10MHz(2))
#define configPD2_OUT_OD_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_2MHz(2))
#define configPD2_OUT_OD_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_50MHz(2))
#define configPD2_AF_PP_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_10MHz(2))
#define configPD2_AF_PP_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_2MHz(2))
#define configPD2_AF_PP_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_50MHz(2))
#define configPD2_AF_OD_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_10MHz(2))
#define configPD2_AF_OD_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_2MHz(2))
#define configPD2_AF_OD_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_50MHz(2))


/*******************************  PD3 configuration define *******************************/
#define configPD3_AIN           (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_AIN(3))
#define configPD3_IN_FLOATING   (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_IN_FLOATING(3))
#define configPD3_IPU           (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->BSRR|= GPIO_Pin_3,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPD3_IPD           (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->BRR |= GPIO_Pin_3,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPD3_OUT_PP_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_10MHz(3))
#define configPD3_OUT_PP_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_2MHz(3))
#define configPD3_OUT_PP_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_50MHz(3))
#define configPD3_OUT_OD_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_10MHz(3))
#define configPD3_OUT_OD_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_2MHz(3))
#define configPD3_OUT_OD_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_50MHz(3))
#define configPD3_AF_PP_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_10MHz(3))
#define configPD3_AF_PP_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_2MHz(3))
#define configPD3_AF_PP_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_50MHz(3))
#define configPD3_AF_OD_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_10MHz(3))
#define configPD3_AF_OD_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_2MHz(3))
#define configPD3_AF_OD_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_50MHz(3))


/*******************************  PD4 configuration define *******************************/
#define configPD4_AIN           (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_AIN(4))
#define configPD4_IN_FLOATING   (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_IN_FLOATING(4))
#define configPD4_IPU           (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->BSRR|= GPIO_Pin_4,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPD4_IPD           (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->BRR |= GPIO_Pin_4,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPD4_OUT_PP_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_10MHz(4))
#define configPD4_OUT_PP_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_2MHz(4))
#define configPD4_OUT_PP_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_50MHz(4))
#define configPD4_OUT_OD_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_10MHz(4))
#define configPD4_OUT_OD_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_2MHz(4))
#define configPD4_OUT_OD_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_50MHz(4))
#define configPD4_AF_PP_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_10MHz(4))
#define configPD4_AF_PP_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_2MHz(4))
#define configPD4_AF_PP_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_50MHz(4))
#define configPD4_AF_OD_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_10MHz(4))
#define configPD4_AF_OD_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_2MHz(4))
#define configPD4_AF_OD_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_50MHz(4))


/*******************************  PD5 configuration define *******************************/
#define configPD5_AIN           (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_AIN(5))
#define configPD5_IN_FLOATING   (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_IN_FLOATING(5))
#define configPD5_IPU           (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->BSRR|= GPIO_Pin_5,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPD5_IPD           (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->BRR |= GPIO_Pin_5,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPD5_OUT_PP_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_10MHz(5))
#define configPD5_OUT_PP_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_2MHz(5))
#define configPD5_OUT_PP_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_50MHz(5))
#define configPD5_OUT_OD_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_10MHz(5))
#define configPD5_OUT_OD_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_2MHz(5))
#define configPD5_OUT_OD_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_50MHz(5))
#define configPD5_AF_PP_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_10MHz(5))
#define configPD5_AF_PP_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_2MHz(5))
#define configPD5_AF_PP_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_50MHz(5))
#define configPD5_AF_OD_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_10MHz(5))
#define configPD5_AF_OD_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_2MHz(5))
#define configPD5_AF_OD_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_50MHz(5))


/*******************************  PD6 configuration define *******************************/
#define configPD6_AIN           (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_AIN(6))
#define configPD6_IN_FLOATING   (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_IN_FLOATING(6))
#define configPD6_IPU           (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->BSRR|= GPIO_Pin_6,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPD6_IPD           (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->BRR |= GPIO_Pin_6,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPD6_OUT_PP_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_10MHz(6))
#define configPD6_OUT_PP_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_2MHz(6))
#define configPD6_OUT_PP_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_50MHz(6))
#define configPD6_OUT_OD_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_10MHz(6))
#define configPD6_OUT_OD_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_2MHz(6))
#define configPD6_OUT_OD_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_50MHz(6))
#define configPD6_AF_PP_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_10MHz(6))
#define configPD6_AF_PP_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_2MHz(6))
#define configPD6_AF_PP_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_50MHz(6))
#define configPD6_AF_OD_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_10MHz(6))
#define configPD6_AF_OD_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_2MHz(6))
#define configPD6_AF_OD_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_50MHz(6))


/*******************************  PD7 configuration define *******************************/
#define configPD7_AIN           (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_AIN(7))
#define configPD7_IN_FLOATING   (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_IN_FLOATING(7))
#define configPD7_IPU           (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->BSRR|= GPIO_Pin_7,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPD7_IPD           (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->BRR |= GPIO_Pin_7,  GPIOD->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPD7_OUT_PP_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_10MHz(7))
#define configPD7_OUT_PP_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_2MHz(7))
#define configPD7_OUT_PP_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_OUT_PP_50MHz(7))
#define configPD7_OUT_OD_10MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_10MHz(7))
#define configPD7_OUT_OD_2MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_2MHz(7))
#define configPD7_OUT_OD_50MHz  (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_OUT_OD_50MHz(7))
#define configPD7_AF_PP_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_10MHz(7))
#define configPD7_AF_PP_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_2MHz(7))
#define configPD7_AF_PP_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_AF_PP_50MHz(7))
#define configPD7_AF_OD_10MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_10MHz(7))
#define configPD7_AF_OD_2MHz    (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_2MHz(7))
#define configPD7_AF_OD_50MHz   (GPIOD->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOD->CRL |= PIN_CONFIG_AF_OD_50MHz(7))


/*******************************  PD8 configuration define *******************************/
#define configPD8_AIN           (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_AIN(8))
#define configPD8_IN_FLOATING   (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_IN_FLOATING(8))
#define configPD8_IPU           (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->BSRR|= GPIO_Pin_8,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPD8_IPD           (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->BRR |= GPIO_Pin_8,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPD8_OUT_PP_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_10MHz(8))
#define configPD8_OUT_PP_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_2MHz(8))
#define configPD8_OUT_PP_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_50MHz(8))
#define configPD8_OUT_OD_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_10MHz(8))
#define configPD8_OUT_OD_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_2MHz(8))
#define configPD8_OUT_OD_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_50MHz(8))
#define configPD8_AF_PP_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_10MHz(8))
#define configPD8_AF_PP_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_2MHz(8))
#define configPD8_AF_PP_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_50MHz(8))
#define configPD8_AF_OD_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_10MHz(8))
#define configPD8_AF_OD_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_2MHz(8))
#define configPD8_AF_OD_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_50MHz(8))


/*******************************  PD9 configuration define *******************************/
#define configPD9_AIN           (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_AIN(9))
#define configPD9_IN_FLOATING   (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_IN_FLOATING(9))
#define configPD9_IPU           (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->BSRR|= GPIO_Pin_9,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPD9_IPD           (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->BRR |= GPIO_Pin_9,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPD9_OUT_PP_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_10MHz(9))
#define configPD9_OUT_PP_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_2MHz(9))
#define configPD9_OUT_PP_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_50MHz(9))
#define configPD9_OUT_OD_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_10MHz(9))
#define configPD9_OUT_OD_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_2MHz(9))
#define configPD9_OUT_OD_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_50MHz(9))
#define configPD9_AF_PP_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_10MHz(9))
#define configPD9_AF_PP_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_2MHz(9))
#define configPD9_AF_PP_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_50MHz(9))
#define configPD9_AF_OD_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_10MHz(9))
#define configPD9_AF_OD_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_2MHz(9))
#define configPD9_AF_OD_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_50MHz(9))


/*******************************  PD10 configuration define *******************************/
#define configPD10_AIN           (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_AIN(10))
#define configPD10_IN_FLOATING   (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_IN_FLOATING(10))
#define configPD10_IPU           (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->BSRR|= GPIO_Pin_10,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPD10_IPD           (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->BRR |= GPIO_Pin_10,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPD10_OUT_PP_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_10MHz(10))
#define configPD10_OUT_PP_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_2MHz(10))
#define configPD10_OUT_PP_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_50MHz(10))
#define configPD10_OUT_OD_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_10MHz(10))
#define configPD10_OUT_OD_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_2MHz(10))
#define configPD10_OUT_OD_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_50MHz(10))
#define configPD10_AF_PP_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_10MHz(10))
#define configPD10_AF_PP_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_2MHz(10))
#define configPD10_AF_PP_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_50MHz(10))
#define configPD10_AF_OD_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_10MHz(10))
#define configPD10_AF_OD_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_2MHz(10))
#define configPD10_AF_OD_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_50MHz(10))


/*******************************  PD11 configuration define *******************************/
#define configPD11_AIN           (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_AIN(11))
#define configPD11_IN_FLOATING   (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_IN_FLOATING(11))
#define configPD11_IPU           (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->BSRR|= GPIO_Pin_11,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPD11_IPD           (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->BRR |= GPIO_Pin_11,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPD11_OUT_PP_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_10MHz(11))
#define configPD11_OUT_PP_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_2MHz(11))
#define configPD11_OUT_PP_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_50MHz(11))
#define configPD11_OUT_OD_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_10MHz(11))
#define configPD11_OUT_OD_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_2MHz(11))
#define configPD11_OUT_OD_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_50MHz(11))
#define configPD11_AF_PP_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_10MHz(11))
#define configPD11_AF_PP_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_2MHz(11))
#define configPD11_AF_PP_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_50MHz(11))
#define configPD11_AF_OD_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_10MHz(11))
#define configPD11_AF_OD_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_2MHz(11))
#define configPD11_AF_OD_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_50MHz(11))


/*******************************  PD12 configuration define *******************************/
#define configPD12_AIN           (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_AIN(12))
#define configPD12_IN_FLOATING   (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_IN_FLOATING(12))
#define configPD12_IPU           (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->BSRR|= GPIO_Pin_12,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPD12_IPD           (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->BRR |= GPIO_Pin_12,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPD12_OUT_PP_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_10MHz(12))
#define configPD12_OUT_PP_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_2MHz(12))
#define configPD12_OUT_PP_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_50MHz(12))
#define configPD12_OUT_OD_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_10MHz(12))
#define configPD12_OUT_OD_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_2MHz(12))
#define configPD12_OUT_OD_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_50MHz(12))
#define configPD12_AF_PP_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_10MHz(12))
#define configPD12_AF_PP_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_2MHz(12))
#define configPD12_AF_PP_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_50MHz(12))
#define configPD12_AF_OD_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_10MHz(12))
#define configPD12_AF_OD_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_2MHz(12))
#define configPD12_AF_OD_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_50MHz(12))


/*******************************  PD13 configuration define *******************************/
#define configPD13_AIN           (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_AIN(13))
#define configPD13_IN_FLOATING   (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_IN_FLOATING(13))
#define configPD13_IPU           (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->BSRR|= GPIO_Pin_13,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPD13_IPD           (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->BRR |= GPIO_Pin_13,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPD13_OUT_PP_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_10MHz(13))
#define configPD13_OUT_PP_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_2MHz(13))
#define configPD13_OUT_PP_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_50MHz(13))
#define configPD13_OUT_OD_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_10MHz(13))
#define configPD13_OUT_OD_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_2MHz(13))
#define configPD13_OUT_OD_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_50MHz(13))
#define configPD13_AF_PP_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_10MHz(13))
#define configPD13_AF_PP_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_2MHz(13))
#define configPD13_AF_PP_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_50MHz(13))
#define configPD13_AF_OD_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_10MHz(13))
#define configPD13_AF_OD_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_2MHz(13))
#define configPD13_AF_OD_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_50MHz(13))


/*******************************  PD14 configuration define *******************************/
#define configPD14_AIN           (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_AIN(14))
#define configPD14_IN_FLOATING   (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_IN_FLOATING(14))
#define configPD14_IPU           (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->BSRR|= GPIO_Pin_14,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPD14_IPD           (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->BRR |= GPIO_Pin_14,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPD14_OUT_PP_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_10MHz(14))
#define configPD14_OUT_PP_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_2MHz(14))
#define configPD14_OUT_PP_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_50MHz(14))
#define configPD14_OUT_OD_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_10MHz(14))
#define configPD14_OUT_OD_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_2MHz(14))
#define configPD14_OUT_OD_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_50MHz(14))
#define configPD14_AF_PP_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_10MHz(14))
#define configPD14_AF_PP_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_2MHz(14))
#define configPD14_AF_PP_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_50MHz(14))
#define configPD14_AF_OD_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_10MHz(14))
#define configPD14_AF_OD_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_2MHz(14))
#define configPD14_AF_OD_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_50MHz(14))


/*******************************  PD15 configuration define *******************************/
#define configPD15_AIN           (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_AIN(15))
#define configPD15_IN_FLOATING   (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_IN_FLOATING(15))
#define configPD15_IPU           (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->BSRR|= GPIO_Pin_15,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPD15_IPD           (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->BRR |= GPIO_Pin_15,  GPIOD->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPD15_OUT_PP_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_10MHz(15))
#define configPD15_OUT_PP_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_2MHz(15))
#define configPD15_OUT_PP_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_OUT_PP_50MHz(15))
#define configPD15_OUT_OD_10MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_10MHz(15))
#define configPD15_OUT_OD_2MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_2MHz(15))
#define configPD15_OUT_OD_50MHz  (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_OUT_OD_50MHz(15))
#define configPD15_AF_PP_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_10MHz(15))
#define configPD15_AF_PP_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_2MHz(15))
#define configPD15_AF_PP_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_AF_PP_50MHz(15))
#define configPD15_AF_OD_10MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_10MHz(15))
#define configPD15_AF_OD_2MHz    (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_2MHz(15))
#define configPD15_AF_OD_50MHz   (GPIOD->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOD->CRH |= PIN_CONFIG_AF_OD_50MHz(15))


/*******************************  PE0 configuration define *******************************/
#define configPE0_AIN           (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_AIN(0))
#define configPE0_IN_FLOATING   (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_IN_FLOATING(0))
#define configPE0_IPU           (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->BSRR|= GPIO_Pin_0,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPE0_IPD           (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->BRR |= GPIO_Pin_0,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPE0_OUT_PP_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_10MHz(0))
#define configPE0_OUT_PP_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_2MHz(0))
#define configPE0_OUT_PP_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_50MHz(0))
#define configPE0_OUT_OD_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_10MHz(0))
#define configPE0_OUT_OD_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_2MHz(0))
#define configPE0_OUT_OD_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_50MHz(0))
#define configPE0_AF_PP_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_10MHz(0))
#define configPE0_AF_PP_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_2MHz(0))
#define configPE0_AF_PP_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_50MHz(0))
#define configPE0_AF_OD_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_10MHz(0))
#define configPE0_AF_OD_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_2MHz(0))
#define configPE0_AF_OD_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_50MHz(0))


/*******************************  PE1 configuration define *******************************/
#define configPE1_AIN           (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_AIN(1))
#define configPE1_IN_FLOATING   (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_IN_FLOATING(1))
#define configPE1_IPU           (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->BSRR|= GPIO_Pin_1,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPE1_IPD           (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->BRR |= GPIO_Pin_1,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPE1_OUT_PP_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_10MHz(1))
#define configPE1_OUT_PP_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_2MHz(1))
#define configPE1_OUT_PP_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_50MHz(1))
#define configPE1_OUT_OD_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_10MHz(1))
#define configPE1_OUT_OD_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_2MHz(1))
#define configPE1_OUT_OD_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_50MHz(1))
#define configPE1_AF_PP_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_10MHz(1))
#define configPE1_AF_PP_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_2MHz(1))
#define configPE1_AF_PP_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_50MHz(1))
#define configPE1_AF_OD_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_10MHz(1))
#define configPE1_AF_OD_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_2MHz(1))
#define configPE1_AF_OD_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_50MHz(1))


/*******************************  PE2 configuration define *******************************/
#define configPE2_AIN           (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_AIN(2))
#define configPE2_IN_FLOATING   (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_IN_FLOATING(2))
#define configPE2_IPU           (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->BSRR|= GPIO_Pin_2,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPE2_IPD           (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->BRR |= GPIO_Pin_2,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPE2_OUT_PP_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_10MHz(2))
#define configPE2_OUT_PP_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_2MHz(2))
#define configPE2_OUT_PP_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_50MHz(2))
#define configPE2_OUT_OD_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_10MHz(2))
#define configPE2_OUT_OD_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_2MHz(2))
#define configPE2_OUT_OD_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_50MHz(2))
#define configPE2_AF_PP_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_10MHz(2))
#define configPE2_AF_PP_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_2MHz(2))
#define configPE2_AF_PP_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_50MHz(2))
#define configPE2_AF_OD_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_10MHz(2))
#define configPE2_AF_OD_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_2MHz(2))
#define configPE2_AF_OD_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_50MHz(2))


/*******************************  PE3 configuration define *******************************/
#define configPE3_AIN           (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_AIN(3))
#define configPE3_IN_FLOATING   (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_IN_FLOATING(3))
#define configPE3_IPU           (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->BSRR|= GPIO_Pin_3,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPE3_IPD           (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->BRR |= GPIO_Pin_3,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPE3_OUT_PP_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_10MHz(3))
#define configPE3_OUT_PP_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_2MHz(3))
#define configPE3_OUT_PP_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_50MHz(3))
#define configPE3_OUT_OD_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_10MHz(3))
#define configPE3_OUT_OD_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_2MHz(3))
#define configPE3_OUT_OD_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_50MHz(3))
#define configPE3_AF_PP_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_10MHz(3))
#define configPE3_AF_PP_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_2MHz(3))
#define configPE3_AF_PP_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_50MHz(3))
#define configPE3_AF_OD_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_10MHz(3))
#define configPE3_AF_OD_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_2MHz(3))
#define configPE3_AF_OD_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_50MHz(3))


/*******************************  PE4 configuration define *******************************/
#define configPE4_AIN           (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_AIN(4))
#define configPE4_IN_FLOATING   (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_IN_FLOATING(4))
#define configPE4_IPU           (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->BSRR|= GPIO_Pin_4,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPE4_IPD           (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->BRR |= GPIO_Pin_4,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPE4_OUT_PP_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_10MHz(4))
#define configPE4_OUT_PP_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_2MHz(4))
#define configPE4_OUT_PP_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_50MHz(4))
#define configPE4_OUT_OD_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_10MHz(4))
#define configPE4_OUT_OD_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_2MHz(4))
#define configPE4_OUT_OD_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_50MHz(4))
#define configPE4_AF_PP_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_10MHz(4))
#define configPE4_AF_PP_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_2MHz(4))
#define configPE4_AF_PP_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_50MHz(4))
#define configPE4_AF_OD_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_10MHz(4))
#define configPE4_AF_OD_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_2MHz(4))
#define configPE4_AF_OD_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_50MHz(4))


/*******************************  PE5 configuration define *******************************/
#define configPE5_AIN           (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_AIN(5))
#define configPE5_IN_FLOATING   (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_IN_FLOATING(5))
#define configPE5_IPU           (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->BSRR|= GPIO_Pin_5,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPE5_IPD           (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->BRR |= GPIO_Pin_5,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPE5_OUT_PP_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_10MHz(5))
#define configPE5_OUT_PP_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_2MHz(5))
#define configPE5_OUT_PP_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_50MHz(5))
#define configPE5_OUT_OD_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_10MHz(5))
#define configPE5_OUT_OD_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_2MHz(5))
#define configPE5_OUT_OD_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_50MHz(5))
#define configPE5_AF_PP_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_10MHz(5))
#define configPE5_AF_PP_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_2MHz(5))
#define configPE5_AF_PP_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_50MHz(5))
#define configPE5_AF_OD_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_10MHz(5))
#define configPE5_AF_OD_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_2MHz(5))
#define configPE5_AF_OD_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_50MHz(5))


/*******************************  PE6 configuration define *******************************/
#define configPE6_AIN           (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_AIN(6))
#define configPE6_IN_FLOATING   (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_IN_FLOATING(6))
#define configPE6_IPU           (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->BSRR|= GPIO_Pin_6,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPE6_IPD           (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->BRR |= GPIO_Pin_6,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPE6_OUT_PP_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_10MHz(6))
#define configPE6_OUT_PP_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_2MHz(6))
#define configPE6_OUT_PP_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_50MHz(6))
#define configPE6_OUT_OD_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_10MHz(6))
#define configPE6_OUT_OD_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_2MHz(6))
#define configPE6_OUT_OD_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_50MHz(6))
#define configPE6_AF_PP_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_10MHz(6))
#define configPE6_AF_PP_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_2MHz(6))
#define configPE6_AF_PP_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_50MHz(6))
#define configPE6_AF_OD_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_10MHz(6))
#define configPE6_AF_OD_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_2MHz(6))
#define configPE6_AF_OD_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_50MHz(6))


/*******************************  PE7 configuration define *******************************/
#define configPE7_AIN           (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_AIN(7))
#define configPE7_IN_FLOATING   (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_IN_FLOATING(7))
#define configPE7_IPU           (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->BSRR|= GPIO_Pin_7,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPE7_IPD           (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->BRR |= GPIO_Pin_7,  GPIOE->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPE7_OUT_PP_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_10MHz(7))
#define configPE7_OUT_PP_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_2MHz(7))
#define configPE7_OUT_PP_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_OUT_PP_50MHz(7))
#define configPE7_OUT_OD_10MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_10MHz(7))
#define configPE7_OUT_OD_2MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_2MHz(7))
#define configPE7_OUT_OD_50MHz  (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_OUT_OD_50MHz(7))
#define configPE7_AF_PP_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_10MHz(7))
#define configPE7_AF_PP_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_2MHz(7))
#define configPE7_AF_PP_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_AF_PP_50MHz(7))
#define configPE7_AF_OD_10MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_10MHz(7))
#define configPE7_AF_OD_2MHz    (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_2MHz(7))
#define configPE7_AF_OD_50MHz   (GPIOE->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOE->CRL |= PIN_CONFIG_AF_OD_50MHz(7))


/*******************************  PE8 configuration define *******************************/
#define configPE8_AIN           (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_AIN(8))
#define configPE8_IN_FLOATING   (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_IN_FLOATING(8))
#define configPE8_IPU           (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->BSRR|= GPIO_Pin_8,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPE8_IPD           (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->BRR |= GPIO_Pin_8,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPE8_OUT_PP_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_10MHz(8))
#define configPE8_OUT_PP_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_2MHz(8))
#define configPE8_OUT_PP_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_50MHz(8))
#define configPE8_OUT_OD_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_10MHz(8))
#define configPE8_OUT_OD_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_2MHz(8))
#define configPE8_OUT_OD_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_50MHz(8))
#define configPE8_AF_PP_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_10MHz(8))
#define configPE8_AF_PP_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_2MHz(8))
#define configPE8_AF_PP_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_50MHz(8))
#define configPE8_AF_OD_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_10MHz(8))
#define configPE8_AF_OD_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_2MHz(8))
#define configPE8_AF_OD_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_50MHz(8))


/*******************************  PE9 configuration define *******************************/
#define configPE9_AIN           (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_AIN(9))
#define configPE9_IN_FLOATING   (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_IN_FLOATING(9))
#define configPE9_IPU           (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->BSRR|= GPIO_Pin_9,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPE9_IPD           (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->BRR |= GPIO_Pin_9,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPE9_OUT_PP_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_10MHz(9))
#define configPE9_OUT_PP_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_2MHz(9))
#define configPE9_OUT_PP_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_50MHz(9))
#define configPE9_OUT_OD_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_10MHz(9))
#define configPE9_OUT_OD_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_2MHz(9))
#define configPE9_OUT_OD_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_50MHz(9))
#define configPE9_AF_PP_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_10MHz(9))
#define configPE9_AF_PP_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_2MHz(9))
#define configPE9_AF_PP_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_50MHz(9))
#define configPE9_AF_OD_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_10MHz(9))
#define configPE9_AF_OD_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_2MHz(9))
#define configPE9_AF_OD_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_50MHz(9))


/*******************************  PE10 configuration define *******************************/
#define configPE10_AIN           (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_AIN(10))
#define configPE10_IN_FLOATING   (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_IN_FLOATING(10))
#define configPE10_IPU           (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->BSRR|= GPIO_Pin_10,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPE10_IPD           (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->BRR |= GPIO_Pin_10,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPE10_OUT_PP_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_10MHz(10))
#define configPE10_OUT_PP_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_2MHz(10))
#define configPE10_OUT_PP_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_50MHz(10))
#define configPE10_OUT_OD_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_10MHz(10))
#define configPE10_OUT_OD_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_2MHz(10))
#define configPE10_OUT_OD_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_50MHz(10))
#define configPE10_AF_PP_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_10MHz(10))
#define configPE10_AF_PP_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_2MHz(10))
#define configPE10_AF_PP_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_50MHz(10))
#define configPE10_AF_OD_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_10MHz(10))
#define configPE10_AF_OD_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_2MHz(10))
#define configPE10_AF_OD_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_50MHz(10))


/*******************************  PE11 configuration define *******************************/
#define configPE11_AIN           (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_AIN(11))
#define configPE11_IN_FLOATING   (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_IN_FLOATING(11))
#define configPE11_IPU           (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->BSRR|= GPIO_Pin_11,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPE11_IPD           (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->BRR |= GPIO_Pin_11,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPE11_OUT_PP_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_10MHz(11))
#define configPE11_OUT_PP_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_2MHz(11))
#define configPE11_OUT_PP_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_50MHz(11))
#define configPE11_OUT_OD_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_10MHz(11))
#define configPE11_OUT_OD_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_2MHz(11))
#define configPE11_OUT_OD_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_50MHz(11))
#define configPE11_AF_PP_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_10MHz(11))
#define configPE11_AF_PP_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_2MHz(11))
#define configPE11_AF_PP_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_50MHz(11))
#define configPE11_AF_OD_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_10MHz(11))
#define configPE11_AF_OD_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_2MHz(11))
#define configPE11_AF_OD_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_50MHz(11))


/*******************************  PE12 configuration define *******************************/
#define configPE12_AIN           (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_AIN(12))
#define configPE12_IN_FLOATING   (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_IN_FLOATING(12))
#define configPE12_IPU           (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->BSRR|= GPIO_Pin_12,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPE12_IPD           (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->BRR |= GPIO_Pin_12,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPE12_OUT_PP_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_10MHz(12))
#define configPE12_OUT_PP_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_2MHz(12))
#define configPE12_OUT_PP_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_50MHz(12))
#define configPE12_OUT_OD_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_10MHz(12))
#define configPE12_OUT_OD_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_2MHz(12))
#define configPE12_OUT_OD_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_50MHz(12))
#define configPE12_AF_PP_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_10MHz(12))
#define configPE12_AF_PP_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_2MHz(12))
#define configPE12_AF_PP_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_50MHz(12))
#define configPE12_AF_OD_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_10MHz(12))
#define configPE12_AF_OD_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_2MHz(12))
#define configPE12_AF_OD_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_50MHz(12))


/*******************************  PE13 configuration define *******************************/
#define configPE13_AIN           (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_AIN(13))
#define configPE13_IN_FLOATING   (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_IN_FLOATING(13))
#define configPE13_IPU           (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->BSRR|= GPIO_Pin_13,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPE13_IPD           (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->BRR |= GPIO_Pin_13,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPE13_OUT_PP_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_10MHz(13))
#define configPE13_OUT_PP_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_2MHz(13))
#define configPE13_OUT_PP_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_50MHz(13))
#define configPE13_OUT_OD_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_10MHz(13))
#define configPE13_OUT_OD_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_2MHz(13))
#define configPE13_OUT_OD_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_50MHz(13))
#define configPE13_AF_PP_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_10MHz(13))
#define configPE13_AF_PP_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_2MHz(13))
#define configPE13_AF_PP_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_50MHz(13))
#define configPE13_AF_OD_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_10MHz(13))
#define configPE13_AF_OD_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_2MHz(13))
#define configPE13_AF_OD_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_50MHz(13))


/*******************************  PE14 configuration define *******************************/
#define configPE14_AIN           (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_AIN(14))
#define configPE14_IN_FLOATING   (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_IN_FLOATING(14))
#define configPE14_IPU           (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->BSRR|= GPIO_Pin_14,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPE14_IPD           (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->BRR |= GPIO_Pin_14,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPE14_OUT_PP_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_10MHz(14))
#define configPE14_OUT_PP_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_2MHz(14))
#define configPE14_OUT_PP_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_50MHz(14))
#define configPE14_OUT_OD_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_10MHz(14))
#define configPE14_OUT_OD_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_2MHz(14))
#define configPE14_OUT_OD_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_50MHz(14))
#define configPE14_AF_PP_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_10MHz(14))
#define configPE14_AF_PP_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_2MHz(14))
#define configPE14_AF_PP_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_50MHz(14))
#define configPE14_AF_OD_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_10MHz(14))
#define configPE14_AF_OD_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_2MHz(14))
#define configPE14_AF_OD_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_50MHz(14))


/*******************************  PE15 configuration define *******************************/
#define configPE15_AIN           (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_AIN(15))
#define configPE15_IN_FLOATING   (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_IN_FLOATING(15))
#define configPE15_IPU           (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->BSRR|= GPIO_Pin_15,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPE15_IPD           (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->BRR |= GPIO_Pin_15,  GPIOE->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPE15_OUT_PP_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_10MHz(15))
#define configPE15_OUT_PP_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_2MHz(15))
#define configPE15_OUT_PP_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_OUT_PP_50MHz(15))
#define configPE15_OUT_OD_10MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_10MHz(15))
#define configPE15_OUT_OD_2MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_2MHz(15))
#define configPE15_OUT_OD_50MHz  (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_OUT_OD_50MHz(15))
#define configPE15_AF_PP_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_10MHz(15))
#define configPE15_AF_PP_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_2MHz(15))
#define configPE15_AF_PP_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_AF_PP_50MHz(15))
#define configPE15_AF_OD_10MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_10MHz(15))
#define configPE15_AF_OD_2MHz    (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_2MHz(15))
#define configPE15_AF_OD_50MHz   (GPIOE->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOE->CRH |= PIN_CONFIG_AF_OD_50MHz(15))


/*******************************  PF0 configuration define *******************************/
#define configPF0_AIN           (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_AIN(0))
#define configPF0_IN_FLOATING   (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_IN_FLOATING(0))
#define configPF0_IPU           (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->BSRR|= GPIO_Pin_0,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPF0_IPD           (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->BRR |= GPIO_Pin_0,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPF0_OUT_PP_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_10MHz(0))
#define configPF0_OUT_PP_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_2MHz(0))
#define configPF0_OUT_PP_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_50MHz(0))
#define configPF0_OUT_OD_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_10MHz(0))
#define configPF0_OUT_OD_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_2MHz(0))
#define configPF0_OUT_OD_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_50MHz(0))
#define configPF0_AF_PP_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_10MHz(0))
#define configPF0_AF_PP_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_2MHz(0))
#define configPF0_AF_PP_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_50MHz(0))
#define configPF0_AF_OD_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_10MHz(0))
#define configPF0_AF_OD_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_2MHz(0))
#define configPF0_AF_OD_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_50MHz(0))


/*******************************  PF1 configuration define *******************************/
#define configPF1_AIN           (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_AIN(1))
#define configPF1_IN_FLOATING   (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_IN_FLOATING(1))
#define configPF1_IPU           (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->BSRR|= GPIO_Pin_1,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPF1_IPD           (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->BRR |= GPIO_Pin_1,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPF1_OUT_PP_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_10MHz(1))
#define configPF1_OUT_PP_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_2MHz(1))
#define configPF1_OUT_PP_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_50MHz(1))
#define configPF1_OUT_OD_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_10MHz(1))
#define configPF1_OUT_OD_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_2MHz(1))
#define configPF1_OUT_OD_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_50MHz(1))
#define configPF1_AF_PP_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_10MHz(1))
#define configPF1_AF_PP_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_2MHz(1))
#define configPF1_AF_PP_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_50MHz(1))
#define configPF1_AF_OD_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_10MHz(1))
#define configPF1_AF_OD_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_2MHz(1))
#define configPF1_AF_OD_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_50MHz(1))


/*******************************  PF2 configuration define *******************************/
#define configPF2_AIN           (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_AIN(2))
#define configPF2_IN_FLOATING   (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_IN_FLOATING(2))
#define configPF2_IPU           (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->BSRR|= GPIO_Pin_2,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPF2_IPD           (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->BRR |= GPIO_Pin_2,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPF2_OUT_PP_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_10MHz(2))
#define configPF2_OUT_PP_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_2MHz(2))
#define configPF2_OUT_PP_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_50MHz(2))
#define configPF2_OUT_OD_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_10MHz(2))
#define configPF2_OUT_OD_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_2MHz(2))
#define configPF2_OUT_OD_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_50MHz(2))
#define configPF2_AF_PP_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_10MHz(2))
#define configPF2_AF_PP_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_2MHz(2))
#define configPF2_AF_PP_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_50MHz(2))
#define configPF2_AF_OD_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_10MHz(2))
#define configPF2_AF_OD_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_2MHz(2))
#define configPF2_AF_OD_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_50MHz(2))


/*******************************  PF3 configuration define *******************************/
#define configPF3_AIN           (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_AIN(3))
#define configPF3_IN_FLOATING   (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_IN_FLOATING(3))
#define configPF3_IPU           (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->BSRR|= GPIO_Pin_3,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPF3_IPD           (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->BRR |= GPIO_Pin_3,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPF3_OUT_PP_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_10MHz(3))
#define configPF3_OUT_PP_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_2MHz(3))
#define configPF3_OUT_PP_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_50MHz(3))
#define configPF3_OUT_OD_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_10MHz(3))
#define configPF3_OUT_OD_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_2MHz(3))
#define configPF3_OUT_OD_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_50MHz(3))
#define configPF3_AF_PP_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_10MHz(3))
#define configPF3_AF_PP_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_2MHz(3))
#define configPF3_AF_PP_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_50MHz(3))
#define configPF3_AF_OD_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_10MHz(3))
#define configPF3_AF_OD_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_2MHz(3))
#define configPF3_AF_OD_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_50MHz(3))


/*******************************  PF4 configuration define *******************************/
#define configPF4_AIN           (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_AIN(4))
#define configPF4_IN_FLOATING   (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_IN_FLOATING(4))
#define configPF4_IPU           (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->BSRR|= GPIO_Pin_4,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPF4_IPD           (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->BRR |= GPIO_Pin_4,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPF4_OUT_PP_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_10MHz(4))
#define configPF4_OUT_PP_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_2MHz(4))
#define configPF4_OUT_PP_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_50MHz(4))
#define configPF4_OUT_OD_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_10MHz(4))
#define configPF4_OUT_OD_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_2MHz(4))
#define configPF4_OUT_OD_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_50MHz(4))
#define configPF4_AF_PP_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_10MHz(4))
#define configPF4_AF_PP_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_2MHz(4))
#define configPF4_AF_PP_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_50MHz(4))
#define configPF4_AF_OD_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_10MHz(4))
#define configPF4_AF_OD_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_2MHz(4))
#define configPF4_AF_OD_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_50MHz(4))


/*******************************  PF5 configuration define *******************************/
#define configPF5_AIN           (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_AIN(5))
#define configPF5_IN_FLOATING   (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_IN_FLOATING(5))
#define configPF5_IPU           (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->BSRR|= GPIO_Pin_5,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPF5_IPD           (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->BRR |= GPIO_Pin_5,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPF5_OUT_PP_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_10MHz(5))
#define configPF5_OUT_PP_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_2MHz(5))
#define configPF5_OUT_PP_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_50MHz(5))
#define configPF5_OUT_OD_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_10MHz(5))
#define configPF5_OUT_OD_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_2MHz(5))
#define configPF5_OUT_OD_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_50MHz(5))
#define configPF5_AF_PP_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_10MHz(5))
#define configPF5_AF_PP_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_2MHz(5))
#define configPF5_AF_PP_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_50MHz(5))
#define configPF5_AF_OD_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_10MHz(5))
#define configPF5_AF_OD_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_2MHz(5))
#define configPF5_AF_OD_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_50MHz(5))


/*******************************  PF6 configuration define *******************************/
#define configPF6_AIN           (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_AIN(6))
#define configPF6_IN_FLOATING   (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_IN_FLOATING(6))
#define configPF6_IPU           (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->BSRR|= GPIO_Pin_6,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPF6_IPD           (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->BRR |= GPIO_Pin_6,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPF6_OUT_PP_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_10MHz(6))
#define configPF6_OUT_PP_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_2MHz(6))
#define configPF6_OUT_PP_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_50MHz(6))
#define configPF6_OUT_OD_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_10MHz(6))
#define configPF6_OUT_OD_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_2MHz(6))
#define configPF6_OUT_OD_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_50MHz(6))
#define configPF6_AF_PP_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_10MHz(6))
#define configPF6_AF_PP_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_2MHz(6))
#define configPF6_AF_PP_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_50MHz(6))
#define configPF6_AF_OD_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_10MHz(6))
#define configPF6_AF_OD_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_2MHz(6))
#define configPF6_AF_OD_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_50MHz(6))


/*******************************  PF7 configuration define *******************************/
#define configPF7_AIN           (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_AIN(7))
#define configPF7_IN_FLOATING   (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_IN_FLOATING(7))
#define configPF7_IPU           (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->BSRR|= GPIO_Pin_7,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPF7_IPD           (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->BRR |= GPIO_Pin_7,  GPIOF->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPF7_OUT_PP_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_10MHz(7))
#define configPF7_OUT_PP_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_2MHz(7))
#define configPF7_OUT_PP_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_OUT_PP_50MHz(7))
#define configPF7_OUT_OD_10MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_10MHz(7))
#define configPF7_OUT_OD_2MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_2MHz(7))
#define configPF7_OUT_OD_50MHz  (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_OUT_OD_50MHz(7))
#define configPF7_AF_PP_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_10MHz(7))
#define configPF7_AF_PP_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_2MHz(7))
#define configPF7_AF_PP_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_AF_PP_50MHz(7))
#define configPF7_AF_OD_10MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_10MHz(7))
#define configPF7_AF_OD_2MHz    (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_2MHz(7))
#define configPF7_AF_OD_50MHz   (GPIOF->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOF->CRL |= PIN_CONFIG_AF_OD_50MHz(7))


/*******************************  PF8 configuration define *******************************/
#define configPF8_AIN           (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_AIN(8))
#define configPF8_IN_FLOATING   (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_IN_FLOATING(8))
#define configPF8_IPU           (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->BSRR|= GPIO_Pin_8,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPF8_IPD           (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->BRR |= GPIO_Pin_8,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPF8_OUT_PP_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_10MHz(8))
#define configPF8_OUT_PP_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_2MHz(8))
#define configPF8_OUT_PP_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_50MHz(8))
#define configPF8_OUT_OD_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_10MHz(8))
#define configPF8_OUT_OD_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_2MHz(8))
#define configPF8_OUT_OD_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_50MHz(8))
#define configPF8_AF_PP_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_10MHz(8))
#define configPF8_AF_PP_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_2MHz(8))
#define configPF8_AF_PP_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_50MHz(8))
#define configPF8_AF_OD_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_10MHz(8))
#define configPF8_AF_OD_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_2MHz(8))
#define configPF8_AF_OD_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_50MHz(8))


/*******************************  PF9 configuration define *******************************/
#define configPF9_AIN           (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_AIN(9))
#define configPF9_IN_FLOATING   (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_IN_FLOATING(9))
#define configPF9_IPU           (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->BSRR|= GPIO_Pin_9,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPF9_IPD           (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->BRR |= GPIO_Pin_9,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPF9_OUT_PP_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_10MHz(9))
#define configPF9_OUT_PP_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_2MHz(9))
#define configPF9_OUT_PP_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_50MHz(9))
#define configPF9_OUT_OD_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_10MHz(9))
#define configPF9_OUT_OD_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_2MHz(9))
#define configPF9_OUT_OD_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_50MHz(9))
#define configPF9_AF_PP_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_10MHz(9))
#define configPF9_AF_PP_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_2MHz(9))
#define configPF9_AF_PP_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_50MHz(9))
#define configPF9_AF_OD_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_10MHz(9))
#define configPF9_AF_OD_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_2MHz(9))
#define configPF9_AF_OD_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_50MHz(9))


/*******************************  PF10 configuration define *******************************/
#define configPF10_AIN           (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_AIN(10))
#define configPF10_IN_FLOATING   (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_IN_FLOATING(10))
#define configPF10_IPU           (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->BSRR|= GPIO_Pin_10,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPF10_IPD           (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->BRR |= GPIO_Pin_10,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPF10_OUT_PP_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_10MHz(10))
#define configPF10_OUT_PP_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_2MHz(10))
#define configPF10_OUT_PP_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_50MHz(10))
#define configPF10_OUT_OD_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_10MHz(10))
#define configPF10_OUT_OD_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_2MHz(10))
#define configPF10_OUT_OD_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_50MHz(10))
#define configPF10_AF_PP_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_10MHz(10))
#define configPF10_AF_PP_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_2MHz(10))
#define configPF10_AF_PP_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_50MHz(10))
#define configPF10_AF_OD_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_10MHz(10))
#define configPF10_AF_OD_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_2MHz(10))
#define configPF10_AF_OD_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_50MHz(10))


/*******************************  PF11 configuration define *******************************/
#define configPF11_AIN           (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_AIN(11))
#define configPF11_IN_FLOATING   (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_IN_FLOATING(11))
#define configPF11_IPU           (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->BSRR|= GPIO_Pin_11,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPF11_IPD           (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->BRR |= GPIO_Pin_11,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPF11_OUT_PP_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_10MHz(11))
#define configPF11_OUT_PP_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_2MHz(11))
#define configPF11_OUT_PP_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_50MHz(11))
#define configPF11_OUT_OD_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_10MHz(11))
#define configPF11_OUT_OD_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_2MHz(11))
#define configPF11_OUT_OD_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_50MHz(11))
#define configPF11_AF_PP_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_10MHz(11))
#define configPF11_AF_PP_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_2MHz(11))
#define configPF11_AF_PP_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_50MHz(11))
#define configPF11_AF_OD_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_10MHz(11))
#define configPF11_AF_OD_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_2MHz(11))
#define configPF11_AF_OD_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_50MHz(11))


/*******************************  PF12 configuration define *******************************/
#define configPF12_AIN           (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_AIN(12))
#define configPF12_IN_FLOATING   (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_IN_FLOATING(12))
#define configPF12_IPU           (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->BSRR|= GPIO_Pin_12,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPF12_IPD           (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->BRR |= GPIO_Pin_12,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPF12_OUT_PP_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_10MHz(12))
#define configPF12_OUT_PP_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_2MHz(12))
#define configPF12_OUT_PP_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_50MHz(12))
#define configPF12_OUT_OD_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_10MHz(12))
#define configPF12_OUT_OD_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_2MHz(12))
#define configPF12_OUT_OD_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_50MHz(12))
#define configPF12_AF_PP_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_10MHz(12))
#define configPF12_AF_PP_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_2MHz(12))
#define configPF12_AF_PP_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_50MHz(12))
#define configPF12_AF_OD_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_10MHz(12))
#define configPF12_AF_OD_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_2MHz(12))
#define configPF12_AF_OD_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_50MHz(12))


/*******************************  PF13 configuration define *******************************/
#define configPF13_AIN           (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_AIN(13))
#define configPF13_IN_FLOATING   (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_IN_FLOATING(13))
#define configPF13_IPU           (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->BSRR|= GPIO_Pin_13,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPF13_IPD           (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->BRR |= GPIO_Pin_13,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPF13_OUT_PP_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_10MHz(13))
#define configPF13_OUT_PP_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_2MHz(13))
#define configPF13_OUT_PP_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_50MHz(13))
#define configPF13_OUT_OD_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_10MHz(13))
#define configPF13_OUT_OD_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_2MHz(13))
#define configPF13_OUT_OD_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_50MHz(13))
#define configPF13_AF_PP_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_10MHz(13))
#define configPF13_AF_PP_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_2MHz(13))
#define configPF13_AF_PP_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_50MHz(13))
#define configPF13_AF_OD_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_10MHz(13))
#define configPF13_AF_OD_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_2MHz(13))
#define configPF13_AF_OD_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_50MHz(13))


/*******************************  PF14 configuration define *******************************/
#define configPF14_AIN           (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_AIN(14))
#define configPF14_IN_FLOATING   (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_IN_FLOATING(14))
#define configPF14_IPU           (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->BSRR|= GPIO_Pin_14,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPF14_IPD           (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->BRR |= GPIO_Pin_14,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPF14_OUT_PP_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_10MHz(14))
#define configPF14_OUT_PP_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_2MHz(14))
#define configPF14_OUT_PP_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_50MHz(14))
#define configPF14_OUT_OD_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_10MHz(14))
#define configPF14_OUT_OD_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_2MHz(14))
#define configPF14_OUT_OD_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_50MHz(14))
#define configPF14_AF_PP_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_10MHz(14))
#define configPF14_AF_PP_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_2MHz(14))
#define configPF14_AF_PP_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_50MHz(14))
#define configPF14_AF_OD_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_10MHz(14))
#define configPF14_AF_OD_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_2MHz(14))
#define configPF14_AF_OD_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_50MHz(14))


/*******************************  PF15 configuration define *******************************/
#define configPF15_AIN           (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_AIN(15))
#define configPF15_IN_FLOATING   (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_IN_FLOATING(15))
#define configPF15_IPU           (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->BSRR|= GPIO_Pin_15,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPF15_IPD           (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->BRR |= GPIO_Pin_15,  GPIOF->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPF15_OUT_PP_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_10MHz(15))
#define configPF15_OUT_PP_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_2MHz(15))
#define configPF15_OUT_PP_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_OUT_PP_50MHz(15))
#define configPF15_OUT_OD_10MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_10MHz(15))
#define configPF15_OUT_OD_2MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_2MHz(15))
#define configPF15_OUT_OD_50MHz  (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_OUT_OD_50MHz(15))
#define configPF15_AF_PP_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_10MHz(15))
#define configPF15_AF_PP_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_2MHz(15))
#define configPF15_AF_PP_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_AF_PP_50MHz(15))
#define configPF15_AF_OD_10MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_10MHz(15))
#define configPF15_AF_OD_2MHz    (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_2MHz(15))
#define configPF15_AF_OD_50MHz   (GPIOF->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOF->CRH |= PIN_CONFIG_AF_OD_50MHz(15))


/*******************************  PG0 configuration define *******************************/
#define configPG0_AIN           (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_AIN(0))
#define configPG0_IN_FLOATING   (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_IN_FLOATING(0))
#define configPG0_IPU           (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->BSRR|= GPIO_Pin_0,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPG0_IPD           (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->BRR |= GPIO_Pin_0,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(0))
#define configPG0_OUT_PP_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_10MHz(0))
#define configPG0_OUT_PP_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_2MHz(0))
#define configPG0_OUT_PP_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_50MHz(0))
#define configPG0_OUT_OD_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_10MHz(0))
#define configPG0_OUT_OD_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_2MHz(0))
#define configPG0_OUT_OD_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_50MHz(0))
#define configPG0_AF_PP_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_10MHz(0))
#define configPG0_AF_PP_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_2MHz(0))
#define configPG0_AF_PP_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_50MHz(0))
#define configPG0_AF_OD_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_10MHz(0))
#define configPG0_AF_OD_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_2MHz(0))
#define configPG0_AF_OD_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_50MHz(0))


/*******************************  PG1 configuration define *******************************/
#define configPG1_AIN           (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_AIN(1))
#define configPG1_IN_FLOATING   (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_IN_FLOATING(1))
#define configPG1_IPU           (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->BSRR|= GPIO_Pin_1,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPG1_IPD           (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->BRR |= GPIO_Pin_1,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(1))
#define configPG1_OUT_PP_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_10MHz(1))
#define configPG1_OUT_PP_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_2MHz(1))
#define configPG1_OUT_PP_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_50MHz(1))
#define configPG1_OUT_OD_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_10MHz(1))
#define configPG1_OUT_OD_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_2MHz(1))
#define configPG1_OUT_OD_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_50MHz(1))
#define configPG1_AF_PP_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_10MHz(1))
#define configPG1_AF_PP_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_2MHz(1))
#define configPG1_AF_PP_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_50MHz(1))
#define configPG1_AF_OD_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_10MHz(1))
#define configPG1_AF_OD_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_2MHz(1))
#define configPG1_AF_OD_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(1)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_50MHz(1))


/*******************************  PG2 configuration define *******************************/
#define configPG2_AIN           (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_AIN(2))
#define configPG2_IN_FLOATING   (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_IN_FLOATING(2))
#define configPG2_IPU           (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->BSRR|= GPIO_Pin_2,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPG2_IPD           (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->BRR |= GPIO_Pin_2,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(2))
#define configPG2_OUT_PP_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_10MHz(2))
#define configPG2_OUT_PP_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_2MHz(2))
#define configPG2_OUT_PP_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_50MHz(2))
#define configPG2_OUT_OD_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_10MHz(2))
#define configPG2_OUT_OD_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_2MHz(2))
#define configPG2_OUT_OD_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_50MHz(2))
#define configPG2_AF_PP_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_10MHz(2))
#define configPG2_AF_PP_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_2MHz(2))
#define configPG2_AF_PP_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_50MHz(2))
#define configPG2_AF_OD_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_10MHz(2))
#define configPG2_AF_OD_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_2MHz(2))
#define configPG2_AF_OD_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(2)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_50MHz(2))


/*******************************  PG3 configuration define *******************************/
#define configPG3_AIN           (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_AIN(3))
#define configPG3_IN_FLOATING   (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_IN_FLOATING(3))
#define configPG3_IPU           (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->BSRR|= GPIO_Pin_3,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPG3_IPD           (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->BRR |= GPIO_Pin_3,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(3))
#define configPG3_OUT_PP_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_10MHz(3))
#define configPG3_OUT_PP_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_2MHz(3))
#define configPG3_OUT_PP_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_50MHz(3))
#define configPG3_OUT_OD_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_10MHz(3))
#define configPG3_OUT_OD_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_2MHz(3))
#define configPG3_OUT_OD_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_50MHz(3))
#define configPG3_AF_PP_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_10MHz(3))
#define configPG3_AF_PP_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_2MHz(3))
#define configPG3_AF_PP_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_50MHz(3))
#define configPG3_AF_OD_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_10MHz(3))
#define configPG3_AF_OD_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_2MHz(3))
#define configPG3_AF_OD_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(3)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_50MHz(3))


/*******************************  PG4 configuration define *******************************/
#define configPG4_AIN           (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_AIN(4))
#define configPG4_IN_FLOATING   (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_IN_FLOATING(4))
#define configPG4_IPU           (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->BSRR|= GPIO_Pin_4,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPG4_IPD           (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->BRR |= GPIO_Pin_4,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(4))
#define configPG4_OUT_PP_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_10MHz(4))
#define configPG4_OUT_PP_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_2MHz(4))
#define configPG4_OUT_PP_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_50MHz(4))
#define configPG4_OUT_OD_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_10MHz(4))
#define configPG4_OUT_OD_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_2MHz(4))
#define configPG4_OUT_OD_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_50MHz(4))
#define configPG4_AF_PP_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_10MHz(4))
#define configPG4_AF_PP_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_2MHz(4))
#define configPG4_AF_PP_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_50MHz(4))
#define configPG4_AF_OD_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_10MHz(4))
#define configPG4_AF_OD_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_2MHz(4))
#define configPG4_AF_OD_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(4)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_50MHz(4))


/*******************************  PG5 configuration define *******************************/
#define configPG5_AIN           (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_AIN(5))
#define configPG5_IN_FLOATING   (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_IN_FLOATING(5))
#define configPG5_IPU           (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->BSRR|= GPIO_Pin_5,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPG5_IPD           (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->BRR |= GPIO_Pin_5,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(5))
#define configPG5_OUT_PP_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_10MHz(5))
#define configPG5_OUT_PP_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_2MHz(5))
#define configPG5_OUT_PP_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_50MHz(5))
#define configPG5_OUT_OD_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_10MHz(5))
#define configPG5_OUT_OD_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_2MHz(5))
#define configPG5_OUT_OD_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_50MHz(5))
#define configPG5_AF_PP_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_10MHz(5))
#define configPG5_AF_PP_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_2MHz(5))
#define configPG5_AF_PP_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_50MHz(5))
#define configPG5_AF_OD_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_10MHz(5))
#define configPG5_AF_OD_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_2MHz(5))
#define configPG5_AF_OD_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(5)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_50MHz(5))


/*******************************  PG6 configuration define *******************************/
#define configPG6_AIN           (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_AIN(6))
#define configPG6_IN_FLOATING   (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_IN_FLOATING(6))
#define configPG6_IPU           (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->BSRR|= GPIO_Pin_6,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPG6_IPD           (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->BRR |= GPIO_Pin_6,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(6))
#define configPG6_OUT_PP_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_10MHz(6))
#define configPG6_OUT_PP_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_2MHz(6))
#define configPG6_OUT_PP_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_50MHz(6))
#define configPG6_OUT_OD_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_10MHz(6))
#define configPG6_OUT_OD_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_2MHz(6))
#define configPG6_OUT_OD_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_50MHz(6))
#define configPG6_AF_PP_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_10MHz(6))
#define configPG6_AF_PP_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_2MHz(6))
#define configPG6_AF_PP_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_50MHz(6))
#define configPG6_AF_OD_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_10MHz(6))
#define configPG6_AF_OD_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_2MHz(6))
#define configPG6_AF_OD_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(6)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_50MHz(6))


/*******************************  PG7 configuration define *******************************/
#define configPG7_AIN           (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_AIN(7))
#define configPG7_IN_FLOATING   (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_IN_FLOATING(7))
#define configPG7_IPU           (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->BSRR|= GPIO_Pin_7,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPG7_IPD           (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->BRR |= GPIO_Pin_7,  GPIOG->CRL |= PIN_CONFIG_IN_PULL(7))
#define configPG7_OUT_PP_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_10MHz(7))
#define configPG7_OUT_PP_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_2MHz(7))
#define configPG7_OUT_PP_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_OUT_PP_50MHz(7))
#define configPG7_OUT_OD_10MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_10MHz(7))
#define configPG7_OUT_OD_2MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_2MHz(7))
#define configPG7_OUT_OD_50MHz  (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_OUT_OD_50MHz(7))
#define configPG7_AF_PP_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_10MHz(7))
#define configPG7_AF_PP_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_2MHz(7))
#define configPG7_AF_PP_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_AF_PP_50MHz(7))
#define configPG7_AF_OD_10MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_10MHz(7))
#define configPG7_AF_OD_2MHz    (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_2MHz(7))
#define configPG7_AF_OD_50MHz   (GPIOG->CRL &= (~PIN_CONFIG_MASK(7)),  GPIOG->CRL |= PIN_CONFIG_AF_OD_50MHz(7))


/*******************************  PG8 configuration define *******************************/
#define configPG8_AIN           (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_AIN(8))
#define configPG8_IN_FLOATING   (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_IN_FLOATING(8))
#define configPG8_IPU           (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->BSRR|= GPIO_Pin_8,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPG8_IPD           (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->BRR |= GPIO_Pin_8,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(8))
#define configPG8_OUT_PP_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_10MHz(8))
#define configPG8_OUT_PP_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_2MHz(8))
#define configPG8_OUT_PP_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_50MHz(8))
#define configPG8_OUT_OD_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_10MHz(8))
#define configPG8_OUT_OD_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_2MHz(8))
#define configPG8_OUT_OD_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_50MHz(8))
#define configPG8_AF_PP_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_10MHz(8))
#define configPG8_AF_PP_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_2MHz(8))
#define configPG8_AF_PP_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_50MHz(8))
#define configPG8_AF_OD_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_10MHz(8))
#define configPG8_AF_OD_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_2MHz(8))
#define configPG8_AF_OD_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(8)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_50MHz(8))


/*******************************  PG9 configuration define *******************************/
#define configPG9_AIN           (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_AIN(9))
#define configPG9_IN_FLOATING   (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_IN_FLOATING(9))
#define configPG9_IPU           (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->BSRR|= GPIO_Pin_9,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPG9_IPD           (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->BRR |= GPIO_Pin_9,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(9))
#define configPG9_OUT_PP_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_10MHz(9))
#define configPG9_OUT_PP_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_2MHz(9))
#define configPG9_OUT_PP_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_50MHz(9))
#define configPG9_OUT_OD_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_10MHz(9))
#define configPG9_OUT_OD_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_2MHz(9))
#define configPG9_OUT_OD_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_50MHz(9))
#define configPG9_AF_PP_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_10MHz(9))
#define configPG9_AF_PP_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_2MHz(9))
#define configPG9_AF_PP_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_50MHz(9))
#define configPG9_AF_OD_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_10MHz(9))
#define configPG9_AF_OD_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_2MHz(9))
#define configPG9_AF_OD_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(9)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_50MHz(9))


/*******************************  PG10 configuration define *******************************/
#define configPG10_AIN           (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_AIN(10))
#define configPG10_IN_FLOATING   (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_IN_FLOATING(10))
#define configPG10_IPU           (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->BSRR|= GPIO_Pin_10,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPG10_IPD           (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->BRR |= GPIO_Pin_10,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(10))
#define configPG10_OUT_PP_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_10MHz(10))
#define configPG10_OUT_PP_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_2MHz(10))
#define configPG10_OUT_PP_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_50MHz(10))
#define configPG10_OUT_OD_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_10MHz(10))
#define configPG10_OUT_OD_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_2MHz(10))
#define configPG10_OUT_OD_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_50MHz(10))
#define configPG10_AF_PP_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_10MHz(10))
#define configPG10_AF_PP_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_2MHz(10))
#define configPG10_AF_PP_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_50MHz(10))
#define configPG10_AF_OD_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_10MHz(10))
#define configPG10_AF_OD_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_2MHz(10))
#define configPG10_AF_OD_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(10)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_50MHz(10))


/*******************************  PG11 configuration define *******************************/
#define configPG11_AIN           (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_AIN(11))
#define configPG11_IN_FLOATING   (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_IN_FLOATING(11))
#define configPG11_IPU           (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->BSRR|= GPIO_Pin_11,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPG11_IPD           (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->BRR |= GPIO_Pin_11,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(11))
#define configPG11_OUT_PP_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_10MHz(11))
#define configPG11_OUT_PP_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_2MHz(11))
#define configPG11_OUT_PP_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_50MHz(11))
#define configPG11_OUT_OD_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_10MHz(11))
#define configPG11_OUT_OD_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_2MHz(11))
#define configPG11_OUT_OD_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_50MHz(11))
#define configPG11_AF_PP_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_10MHz(11))
#define configPG11_AF_PP_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_2MHz(11))
#define configPG11_AF_PP_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_50MHz(11))
#define configPG11_AF_OD_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_10MHz(11))
#define configPG11_AF_OD_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_2MHz(11))
#define configPG11_AF_OD_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(11)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_50MHz(11))


/*******************************  PG12 configuration define *******************************/
#define configPG12_AIN           (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_AIN(12))
#define configPG12_IN_FLOATING   (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_IN_FLOATING(12))
#define configPG12_IPU           (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->BSRR|= GPIO_Pin_12,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPG12_IPD           (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->BRR |= GPIO_Pin_12,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(12))
#define configPG12_OUT_PP_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_10MHz(12))
#define configPG12_OUT_PP_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_2MHz(12))
#define configPG12_OUT_PP_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_50MHz(12))
#define configPG12_OUT_OD_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_10MHz(12))
#define configPG12_OUT_OD_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_2MHz(12))
#define configPG12_OUT_OD_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_50MHz(12))
#define configPG12_AF_PP_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_10MHz(12))
#define configPG12_AF_PP_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_2MHz(12))
#define configPG12_AF_PP_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_50MHz(12))
#define configPG12_AF_OD_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_10MHz(12))
#define configPG12_AF_OD_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_2MHz(12))
#define configPG12_AF_OD_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(12)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_50MHz(12))


/*******************************  PG13 configuration define *******************************/
#define configPG13_AIN           (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_AIN(13))
#define configPG13_IN_FLOATING   (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_IN_FLOATING(13))
#define configPG13_IPU           (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->BSRR|= GPIO_Pin_13,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPG13_IPD           (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->BRR |= GPIO_Pin_13,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(13))
#define configPG13_OUT_PP_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_10MHz(13))
#define configPG13_OUT_PP_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_2MHz(13))
#define configPG13_OUT_PP_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_50MHz(13))
#define configPG13_OUT_OD_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_10MHz(13))
#define configPG13_OUT_OD_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_2MHz(13))
#define configPG13_OUT_OD_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_50MHz(13))
#define configPG13_AF_PP_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_10MHz(13))
#define configPG13_AF_PP_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_2MHz(13))
#define configPG13_AF_PP_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_50MHz(13))
#define configPG13_AF_OD_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_10MHz(13))
#define configPG13_AF_OD_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_2MHz(13))
#define configPG13_AF_OD_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(13)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_50MHz(13))


/*******************************  PG14 configuration define *******************************/
#define configPG14_AIN           (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_AIN(14))
#define configPG14_IN_FLOATING   (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_IN_FLOATING(14))
#define configPG14_IPU           (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->BSRR|= GPIO_Pin_14,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPG14_IPD           (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->BRR |= GPIO_Pin_14,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(14))
#define configPG14_OUT_PP_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_10MHz(14))
#define configPG14_OUT_PP_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_2MHz(14))
#define configPG14_OUT_PP_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_50MHz(14))
#define configPG14_OUT_OD_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_10MHz(14))
#define configPG14_OUT_OD_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_2MHz(14))
#define configPG14_OUT_OD_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_50MHz(14))
#define configPG14_AF_PP_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_10MHz(14))
#define configPG14_AF_PP_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_2MHz(14))
#define configPG14_AF_PP_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_50MHz(14))
#define configPG14_AF_OD_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_10MHz(14))
#define configPG14_AF_OD_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_2MHz(14))
#define configPG14_AF_OD_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(14)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_50MHz(14))


/*******************************  PG15 configuration define *******************************/
#define configPG15_AIN           (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_AIN(15))
#define configPG15_IN_FLOATING   (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_IN_FLOATING(15))
#define configPG15_IPU           (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->BSRR|= GPIO_Pin_15,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPG15_IPD           (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->BRR |= GPIO_Pin_15,  GPIOG->CRH |= PIN_CONFIG_IN_PULL(15))
#define configPG15_OUT_PP_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_10MHz(15))
#define configPG15_OUT_PP_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_2MHz(15))
#define configPG15_OUT_PP_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_OUT_PP_50MHz(15))
#define configPG15_OUT_OD_10MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_10MHz(15))
#define configPG15_OUT_OD_2MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_2MHz(15))
#define configPG15_OUT_OD_50MHz  (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_OUT_OD_50MHz(15))
#define configPG15_AF_PP_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_10MHz(15))
#define configPG15_AF_PP_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_2MHz(15))
#define configPG15_AF_PP_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_AF_PP_50MHz(15))
#define configPG15_AF_OD_10MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_10MHz(15))
#define configPG15_AF_OD_2MHz    (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_2MHz(15))
#define configPG15_AF_OD_50MHz   (GPIOG->CRH &= (~PIN_CONFIG_MASK(15)),  GPIOG->CRH |= PIN_CONFIG_AF_OD_50MHz(15))


// 生成以上定义的python脚本
// text = '''
// /*******************************  PA0 configuration define *******************************/
// #define configPA0_AIN           (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AIN(0))
// #define configPA0_IN_FLOATING   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_IN_FLOATING(0))
// #define configPA0_IPU           (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->BSRR|= GPIO_Pin_0,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(0))
// #define configPA0_IPD           (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->BRR |= GPIO_Pin_0,  GPIOA->CRL |= PIN_CONFIG_IN_PULL(0))
// #define configPA0_OUT_PP_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_10MHz(0))
// #define configPA0_OUT_PP_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_2MHz(0))
// #define configPA0_OUT_PP_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_OUT_PP_50MHz(0))
// #define configPA0_OUT_OD_10MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_10MHz(0))
// #define configPA0_OUT_OD_2MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_2MHz(0))
// #define configPA0_OUT_OD_50MHz  (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_OUT_OD_50MHz(0))
// #define configPA0_AF_PP_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_10MHz(0))
// #define configPA0_AF_PP_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_2MHz(0))
// #define configPA0_AF_PP_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AF_PP_50MHz(0))
// #define configPA0_AF_OD_10MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_10MHz(0))
// #define configPA0_AF_OD_2MHz    (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_2MHz(0))
// #define configPA0_AF_OD_50MHz   (GPIOA->CRL &= (~PIN_CONFIG_MASK(0)),  GPIOA->CRL |= PIN_CONFIG_AF_OD_50MHz(0))
// '''

// port = ['A', 'B', 'C', 'D', 'E', 'F', 'G']

// for p in port:
//   for i in range(0, 16):
//     out = text.replace('PA0', 'P%s%d' % (p, i))
//     out = out.replace('GPIOA', 'GPIO%s' % p)
//     out = out.replace('GPIO_Pin_0', 'GPIO_Pin_%d' % i)
//     out = out.replace('(0)', '(%d)' % i)
//     if i>=8:
//       out = out.replace('CRL', 'CRH')
//     print(out)









#endif /* __UTIL_GPIO_H */

